9:00-9:30

Opening Remarks and Welcome

9:30-10:15

Keynote Address
Dr. Shekhar Borkar, Intel Corporation
"Gigascale System Design -- Challenges and Opportunities"

10:15-11:00

Keynote Address
Professor Melvin Breuer, USC
"Error-Tolerance"

11:00-11:45

Keynote Address
Professor E.J. McCluskey, Stanford University
"Digital Integrated Circuit Testing for Art Historians and Test Experts"

11:45-1:00

Lunch

1:00-3:00

Session 1.1
High-Speed and Energy-Efficient Circuit Design

Session 1.2
Energy-Efficient Processor Microarchitecture(1)

Session 1.3
Scan Design and Test

3:00-3:30

Break

3:30-5:30 

Session 2.1
Routing and Floorplanning

Session 2.2
Formal Verification (with tutorial)

Session 2.3 
Signal Integrity and Leakage

8:30-10:30

Session 3.1
High-Performance On-Chip Communication

(invited session)

Session 3.2
Test Generation and Characterization

Session 3.3
Physically-Aware Design Tools

10:30-11:00

Break

11:00-12:30

Session 4.1

Energy-Efficient Processor Microarchitecture(2)

Session 4.2
Power and Timing Optimization

Session 4.3
Novel Processor Design

12:30-1:30

Lunch

1:30-3:00 

Session 5.1
Emerging Technologies (special session)

Session 5.2
Cache Memory Design

3:00-3:30

Break

3:30-5:00 

Session 6.1
Layout-Driven Circuit Optimization

Session 6.2
Instruction-Level Parallelism(1)

Session 6.3
Power Estimation and Minimization

6:00-9:00

Conference Dinner
Doubletree Hotel, San Jose CA

Panel Discussion -- Grid Computing

9:00-10:30

Session 7.1
Formal Verification Techniques

Session 7.2
Networks on Chips

Session 7.3
Novel Processor Architecture

10:30-11:00

Break

11:00-12:30

Session 8.1
Instruction-Level Parallelism(2)

Session 8.2
Topics in Synthesis and Co-Simulation

Session 8.3
Low Power Architecture

12:30-1:30

Lunch

1:30-2:30

Session 9.1
Test Generation

Session 9.2
Network Routing

Session 9.3
Placement and Floorplanning