ICCD 2006 TECHNICAL PROGRAM IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN



		Monday October 2, 2006 Welcome Pranav Ashar Keynote Presentation Computer Architecture in the Many-Core Era Bill Dally Bell Professor of Engineering and Chairman of Computer Science, Stanford University. Founder and Chairman, Stream Processors, Inc. Abstract We are rapidly moving into an era when microprocessors (and SoCs) will have 10s of processors on a single die. In this "many-core" era, we are less concerned with the architecture of individual processors and more concerned with how they are tied together. In particular we are concerned with how on-chip memory is organized to optimize use of the limited off-chip bandwidth and how long off-chip latency is "hidden" from computation. This talk will discuss the challenges of many-core architecture and how the memory organization and management techniques of stream processing can be applied to solve them. Biography Bill Dally is the Willard R. and Inez Kerr Bell Professor of Engineering and the Chairman of the Department of Computer Science at Stanford University. Bill and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Labs Bill contributed to the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. While a Professor at MIT, his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. At Stanford University his group has developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations. Bill has worked with Cray Research and Intel to incorporate many of these innovations in commercial parallel computers, with Avici Systems to incorporate this technology into Internet routers, co-founded Velio Communications to commercialize high-speed signaling technology, and co-founded Stream Processors, Inc. to commercialize stream processor technology. He is a Fellow of the IEEE, a Fellow of the ACM and has received numerous honors including the IEEE Seymour Cray Award and the ACM Maurice Wilkes award. He is chairman of Stream Processors and on the board of directors of Portal Player. He currently leads projects on computer architecture, network architecture, and programming systems. He has published over 170 papers in these areas and is an author of the textbooks, Digital Systems Engineering and Principles and Practices of Interconnection Networks. 1.1 Microarchitecture Optimization Chair: `Tejas Karkhanis, AMD` Long-term Performance Bottleneck Analysis and Prediction Fei Gao and Suleyman Sair Speculative Code Value Specialization Using the Trace Cache Fill Unit Weifeng Zhang, Bradley Calder, Dean Tullsen and Steve Checkoway Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses Jiangjiang Liu, Krishnan Sundaresan and Nihar Mahapatra Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing - ( Short Presentation ) Shuo Wang and Lei Wang A Low Power Highly Associative Cache for Embedded Systems - ( Short Presentation ) Chuanjun Zhang 1.2 Timing Analysis Chair: Florentin Dartu, Synopsys On the Improvement of Statistical Static Timing Analysis Rajesh Garg, Nikhil Jayakumar and Sunil Khatri FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea Ismail and Kip Killpack Reduction of Crosstalk Pessimism using Tendency Graph Approach Murthy Palla, Klaus Koch, Jens Bargfrede, Glesner Manfred and Walter Anheier Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation Ning Mi, Jeffrey Fan and Sheldon Tan 1.3 Advanced Circuits and Interconnections Chair: Srinivas Raghvendra, Synopsys RasP: An Area-efficient, On-chip Network Simon Hollis and Simon W. Moore Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects Yasuhiro Ogasahara, Masanori Hashimoto and Takao Onoye CMOS Comparators for High-Speed and Low-Power Applications - ( Short Presentation ) Eric Menendez, Dumezie Maduike, Rajesh Garg and Sunil Khatri A Reconfigurable CAM Architecture for Network Search Engines Mehrdad Nourani, Deepak Vijayasarathi and Poras Balsara Delay and Area Efficient First-level Cache Soft Error Detection and Correction Karl Mohr and Lawrence Clark Special Session on Nanotechnology - ( I ) Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD Krishnendu Chakrabarty 3.1 Technology-Aware Design Chair: `Suleyman Sair, North Carolina State University` Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy Dan Nicolaescu, Babak Salamat and Alex Veidenbaum Customizable Fault Tolerant Caches for Embedded Processors Subramanian Ramaswamy and Sudhakar Yalamanchili Reduce Register Files Leakage Through Discharging Cells Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang and Youtao Zhang Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution Yi Ma and Huiyang Zhou 3.2 Multiprocessors and Systems-on-Chip Chair: Huiyang Zhou, Univ. of Central Florida Dynamic Co-Processor Architecture for Software Acceleration on CSoCs Abhishek Mitra, Zhi Guo, Anirban Banerjee and Walid Najjar Polaris: A System-Level Roadmap for On-Chip Interconnection Networks Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li and Li-Shiuan Peh A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi and Hamid Sarbazi-Azad Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors Sean Leventhal and Manoj Franklin 3.3 Robust and Low-Power Design Styles Chair: Larry Clark, Arizona State University A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals Kimiyoshi Usami and Naoaki Ohkubo Synthesis of Regular Logic Bricks for Robust IC Design Kim Yaw Tong and Lawrence Pileggi An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks Sanjay Pant and David Blaauw Implementing tile-based chip multiprocessors with GALS clocking styles Zhiyi Yu and Bevan Baas Banquet - Keynote Speaker Fabio Angelillis, VP, Synopsys Incorporated Biography Fabio is Vice President of Engineering in the Silicon Engineering Group at Synopsys. He is responsible for industry leading products in the areas of Mask Data Prep, Manufacturing Yield Management, and DFM. He has 22 years of experience in the development and management of R&D organizations across several EDA product lines. He joined Synopsys through its acquisition of Numerical Technologies, where he was Sr. Vice President of R&D. Prior to this role, he worked at Cadence as Vice President of R&D, responsible for some of the most unique and lucrative products in the area of analog and custom design, including Composer, Virtuoso, Analog Artist, Spectre, and physical verification products. In previous years, he held several engineering and management positions at Teradyne and Hewlett Packard. Fabio received his Degree in Computer Engineering from the University of Florida in 1985. Tuesday October 3, 2006 Special Session on Interconnect Scale in Chip Interconnect requires Network Technology Enno Wein Interconnect Considerations For High Performance Network on Chip Designs Uri Cummings, Fulcrum Microsystems Addressing Multicore Communication Challenges Using NoC Technology Drew Wingard, Sonics Incorporated 5.1 Hardware and Software Scheduling Techniques Chair: `Jiangjiang Liu, Lamar University` Clustering-Based Microcode Compression Edson Borin, Mauricio Breternitz Jr., Youfeng Wu and Guido Araujo Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling Kuo-Su Hsiao and Chung-Ho Chen An Enhancement for a Scheduling Logic Pipelined over two Cycles Ruben Gran, Enric Morancho, Angel Olive and Jose M. Llaberia 5.2 Nanoscale Modeling + Synthesis Chair: Azita Emami, Columbia University Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates Saraju Mohanty and Elias Kougianos Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam and Kaushik Roy Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction Rasit Topaloglu and Andrew Kahng 5.3 Power Issues in Test Chair: Rob Aitken, ARM Power-Constrained SOC Test Schedules through Utilization of Functional Buses Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara RTL Scan Design for Skewed-Load At-speed Test under Power Constraints - ( Short Presentation ) Ho Fai Ko and Nicola Nicolici Power Droop Testing Ilia Polian, Alejandro Czutro, Sandip Kundu and Bernd Becker A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation - ( Short Presentation ) Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang and Kewal Saluja Lunch Panel "Extending the Reach of Formal Verification for Electronic Design" Real Intent, Synopsys, Mentor Graphics, and nVidia Special Session on Hardware Equivalence Scalable Sequential Equivalence Checking across Arbitrary Design Transformations Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman and Geert Janssen Seqver : A Sequential Equivalence Verifier for Hardware Designs Daher Kaiss, Silvian Goldenberg, and Zurab Khasidashvili High-Level vs. RTL Combinational Equivalence: An Introduction Alan Hu 7.1 Functional Verification---Advances and Applications Chair: Jason Baumgartner, IBM Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique Kameshwar Chandrasekar and Michael Hsiao Requirements and Concepts for Transaction Level Assertions Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger and Michael Velten Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug - ( Short Presentation ) Marc Boulé, Jean-Samuel Chenard and Zeljko Zilic Simulation-based functional test justification using a decision-digram-based Boolean data miner - ( Short Presentation ) Charles H.-P. Wen, Onur Guzey and Li-C. Wang 7.2 Application Specific Processing Elements Chair: Jamil Kawa, Synopsys FPGA Implementation of High Speed FIR Filters Using Add and Shift Method Shahnam Mirzaei, Anup Hosangadi and Ryan Kastner FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems - ( Short Presentation ) Osama Al-Khaleel, Chris Papachristou, Frank Wolff and Kiamal Pekmestzi Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture - ( Short Presentation ) Tinoosh Mohsenin and Bevan Baas An Efficient, Scalable Hardware Engine for Boolean SATisfiability Mandar Waghmode, Kanupriya Gulati, Sunil Khatri and Weiping Shi 7.3 Physical Design Chair: Saurabh Adya, Synplicity Power/ground supply network optimization for power-gating Hailin Jiang and Malgorzata Marek-Sadowska A Pattern Generation Technique for Maximizing Power Supply Currents - ( Short Presentation ) Kunal Ganeshpure, Alodeep Sanyal and Sandip Kundu Partial Functional Manipulation Based Wirelength Minimization - ( Short Presentation ) Avijit Dutta and David Z. Pan Iterative-Constructive Standard Cell Placer for High Speed and Low Power Sungjae Kim and Eugene Shragowitz 8.1 Design Techniques and Methods Chair: Mauricio Breternitz Jr.`, Intel` Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths Bita Gorjiara, Mehrdad Reshadi and Daniel Gajski Assertion-Based Microarchitecture Design for Improved Reliability Vimal Reddy, Eric Rotenberg and Ahmed Al-Zawawi High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding Xinmiao Zhang 8.2 System On Chip Design Chair: Roozbeh Jafari, University of California, Berkeley Guiding Architectural SRAM Models - ( Short Presentation ) Banit Agrawal and Timothy Sherwood A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models - ( Short Presentation ) Jinwen Xi and Peixin Zhong Reliability Support for On-Chip Memories Using Networks-on-Chip Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini and Giovanni De Micheli Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems Shaobo Liu, Qinru Qiu and Qing Wu 8.3 Power-Efficient Systems Chair: Dan Sorin, Duke University A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems Chuanjun Zhang System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors Xiaofang Wang and Sotirios Ziavras Improving Power and Data Efficiency with Threaded Memory Modules Frederick A. Ware and Craig Hampel Wednesday October 4, 2006 9.1 Improving test quality Chair: Yervant Zorian, Virage Logic Corporation A New Class of Sequential Circuits with Acyclic Test Generation Complexity Chia Yee Ooi and Hideo Fujiwara Efficient Testing of RF MIMO Transceivers Used in WLAN Applications Erkan Acar and Sule Ozev A theory of Error-Rate Testing - ( Short Presentation ) Shideh Shahidi and Sandeep Gupta Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests - ( Short Presentation ) Dong Xiang, Kaiwei Li, Hideo Fujiwara and Jiaguang Sun 9.2 Architectural Synthesis Chair: Anup Hosangadi, Cadence Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach Hwisung Jung and Massoud Pedram Design and Implementation of Software Objects in Hardware Fu-Chiung Cheng and Hung-Chi Wu An accurate Energy estimation framework for VLIW Processor Cores Sourav Roy, Rajat Bhatia and Ashish Mathur 10.1 Design Practice Chair: `Steve Keckler, University of Texas at Austin` Design and Implementation of the TRIPS Primary Memory System Simha Sethumadhavan, Robert McDonald, Rajagopalan Desikan, Doug Burger and Steve Keckler Implementation and Evaluation of On-Chip Network Architectures - ( Short Presentation ) Paul Gratz, Changkyu Kim, Robert McDonald, Stephen Keckler and Doug Burger Microarchitecture and Performance Analysis of Godson-2 SMT Processor - ( Short Presentation ) Zusong Li, Xianchao Xu, Weiwu Hu and Zhimin Tang Patching Processor Design Errors Satish Narayanasamy, Bruce Carneal and Brad Calder 10.2 Architectural Support for Error Protection Chair: Eric Rotenberg, North Carolina State University Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache Nathan Sadler and Daniel Sorin Architectural Support for Run-Time Validation of Control Flow Transfer Yixin Shi, Sean Dempsey and Gyungho Lee Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection Jin-Yi Wang, Yen-Shiang Shue, T N Vijaykumar and Saurabh Bagchi Lunch Special Session on Nanotechnology - ( II ) R. Iris Bahar, Brown University Trends and Future Directions in Nano Structure Based Computing and Fabrication TOP Web Design: Darshana Merchant