Keynote Address 

1.2.1: VLSI & Technology Plenary, Chair: Larry Pileggi, University of Texas at Austin 

1.2.2: Architecture/Algorithms Plenary, Chair: Bing Sheu, University of Southern California, Los Angeles 

1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin 

1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University 

1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University 

1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories 

1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp. 

1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University 

1.4.4: Simulation, Chair: Derek Beatty, Motorola 

2.1.1: Embedded Systems Plenary, Chair: Rolf Ernst, University of Braunschweig 

2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.

2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola 

2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington 

2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America 

2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin 

2.3.2: Test Pattern Generation, Chair: R. Molyneaux 

2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments 

2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin 

2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer 

2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc. 

 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah 

2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx 

3.1.1: Design & Test Plenary, Chair: Alexander Albicki, University of Rochester

3.1.2: CAD Plenary, Chair: Luc Claesen, IMEC 

3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG 

3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard

3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida 

3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University 

3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center 

3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc. 

3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories 

3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University 

3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation 

3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC 

3.4.3: Application-Specific Processors, Chair: Ashwiai Nanda, Texas Instruments 

3.4.4: Performance Driven Synthesis, Chair: Andreas Kuehlmann, IBM T.J. Watson Research Center 

                        

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