Keynote Address
1.2.1: CAD Plenary, Chair: Luc Claesen, IMEC/Kath. Univ.
1.2.2: Technology Plenary, Chair: Kit Cham, Hewlett-Packard
1.3.1: Verification, Chair: Carl Pixley, Motorola, Inc.
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Enhancing FSM Traversal by Temporary Re-Encoding
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Early Quantification and Partitioned Transition
Relations
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Behavioral Verification of an ATM Switch Fabric
using Implicit Abstract State Enumeration
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Boolean Function Representation Based on Disjoint-Support Decompositions
1.3.2: Design for Test, Chair: Sumit Dasgupta, SEMATECH
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A multiseed counter TPG with performance guarantee
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Design for testability of integrated operational
amplifiers using oscillation-test strategy
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A Design For Test Perspective on I/O Management
1.3.3: Panel: Opportunities and Pitfalls in HDL-Based System Design
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Panel: Opportunities and pitfalls in HDL-based
system design
Chair and Organizer: Rajesh Gupta, University of Illinois at Urbana-Champaign
Panelists: Daniel Gajski, Randy Allen, Yatin Trivedi
1.3.4: Panel: Issues on the Architecture and the Design of Distributed Shared Memory Systems
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Issues on the architecture and the design of
distributed shared memory systems
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Design issues for distributed shared-memory systems
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The Tempest approach to distributed shared memory
1.4.1: Novel Aspects of Scheduling, Chair: Masahiro Fujeta, Fujitsu Laboratories of America, Inc.
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Parallel Algorithms for Force Directed Scheduling of
Flattened and Hierarchical Signal Flow Graphs
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Optimal Selection of Supply Voltages and Level
Conversions During Data Path Scheduling Under Resource Constraints
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Multiplexor Network Generation in High Level
Synthesis
1.4.2: Special Session: Multimedia Systems, Chair and Organizer: Bing Sheu, University of Southern California
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Multimodal query support in database servers
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Evaluation of high speed LAN protocols as multimedia carriers
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A Compact Neural Network Based CDMA Receiver for
Multimedia Wireless Communication
1.4.3: System Design Aspects, Chair: Rabindra (Rob) Roy, NEC USA Research Laboratories
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Space Cutting Approaches for Repairing Memories
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Microarchitectural synthesis of gracefully
degradable, dynamically reconfigurable ASICs
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Pausible Clocking: A First Step Toward Heterogeneous
Systems
1.4.4: Panel
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Processor Design Verification
Chair and Organizer: Andrew Piziali, Texas Instruments
Panelists: Kevin Clague, Willis Hendiey, Tom Kenville, Yossi Malka, Shrenik Mehta, David Reed
Poster Session, Chair: Craig Hunter, Motorola, Inc.
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On the Nature and Inadequacies of Transport Timing
Delay Constructs in VHDL Descriptions
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Arithmetic Pattern Generators for Built-In Self-Test
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Testing of embedded A/D converters in mixed-signal
circuit
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A VLSI array architecture with dynamic frequency
clocking
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An integrated microspacecraft
avionics architecture using 3D multichip module building blocks
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New Challenges for Video Servers: Performance of
Non-Linear Applications under User Choice
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An output-shared buffer ATM switch
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A CAM-Based VLSI Architecture for Shared Buffer ATM
Switch with Fuzzy Controlled Buffer Management
2.1.1: Design and Test Plenary, Chair: Magdy Abadir, Motorola, Inc.
2.1.2: Embedded Systems Plenary, Chair: Rolf Ernst, Technical University of Braunschweig
2.2.1: Data Communication, Chair: John Trotter, AT&T Bell Laboratories
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Design and Implementation of a new Synchronization Method for High-Speed
Cell-based Network Interfaces
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Modeling the Technology Impact on the Design of a Two-Level
Multicomputer Interconnection Network
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MMPacking: A Load and Storage Balancing Algorithm
for Distributed Multimedia Servers
2.2.2: Design Automation for Embedded Systems, Chair: Rolf Ernst, Technical University of Braunschweig
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Memory Hierarchy Synthesis of a Multimedia Embedded
Processor
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High Speed Video Board as a Case Study for
Hardware-Software Co-Design
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VLIW-Processors under Periodic Real Time Constraints
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Embedded Systems Design with Frontend Compilers
2.2.3: Branch Prediction, Chair: Jim Bondi, Texas Instruments
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Microarchitecture Support for Reducing Branch
Penalty in a Supercscaler Processor
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Profile-Driven Generation of Trace Samples
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Branch-Directed and Stride-Based Data Cache
Prefetching
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Global Bus Design of a Bus-Based COMA Multiprocessor
DICE
2.2.4: Automatic Test Pattern Generation, Chairs: Bob Molyneaux, IBM Corporation; Hoon Chang, Soong-Sil University of Korea
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Fault Location Based on Circuit Partitioning
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A Better ATPG Algorithm and Its Design Principles
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Using Functional Information and Strategy Switching
in Sequential ATPG
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Modeling the Difficulty of Sequential Automatic Test
Pattern Generation
2.3.1: VLSI Layout, Chair: Andreas Kuehlmann, IBM Corporation
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Using Genetic Algorithms to Automate System
Implementation in a Novel Three-Dimensional Packaging Technology
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Module Generators for a Regular Analog Layout
2.3.2: Special Session: Motorola Processor Design Session Chair: Nasr Ullah, Organizer: Andy Wolfe
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The Direct-Mapped Instruction Cache for ColdFire
Processors
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A Scalable Resistor-less PLL Design for PowerPCTM
Microprocessors
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Design Tradeoffs and Experience with Motorola
PowerPC™ Migration Tools
2.3.3: Embedded Systems Tutorial, Chair: Rolf Ernst, Technical University of Braunschweig
2.3.4: VLSI Technology and Design, Chair: Kit Cham, Hewlett-Packard
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A Scaling Scheme and Optimization Methodology for
Deep Sub-Micron Interconnect
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Design Methodologies for Tolerating Cell and
Interconnect Faults in FPGAs
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Clock-Delayed Domino for Adder and Combinational
Logic Design
2.4.1: Panel
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Processor Design Tools Integration: Future Challenges
Chair: Pradip Bose, IBM Research
Organizers: Raj Raina, Motorola, Inc., and Ashwini Nanda, IBM Research
Moderator: Raj Raina, Motorola, Inc.
Panelists: Joe Hutt, Jim Bondi, Rick McGeer, Mike Kantrowitz
2.4.2: Panel
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Low voltage and low power: how low can you go?
Chair: Sandip Kundu, IBM Corporation
Organizers: Magdy Abadir, Craig Hunter, Motorola, Inc.
Panelists: John Brews, Uttam Ghoshal, Bob Masleid, Kaushik Roy, Hector Sanchez, Ray Stephany, Jim Thomas
3.1.1: Special Session, Chair: Wayne Wolf, Princeton University
3.1.2: Architecture Plenary, Chair: Pen Yew, University of Minnesota
3.2.1: Verification II, Chair: Gabriel Bischoff, DAC
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A formal verification technique for embedded
software
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Binary decision diagrams on network of workstations
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Distributed Binary Decision Diagrams for
Verification of Large Circuits
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The use of random simulation in formal verification
3.2.2: Minimization Techniques, Chair: Shantanu Ganguly, Motorola, Inc.
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Large Standard Cell Libraries and Their Impact on
Layout Area and Circuit Performance
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Implicit Test Sequences Compaction for Decreasing
Test Application Cost
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Dichotomy-based Model for FSM Power Minimization
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Optimal single probe traversal algorithm for testing
of MCM substrate
3.2.3: Panel
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Influence of Internet Applications on Microarchitecture
Chair and Organizer: Ashwini Nanda, IBM Research
Moderator: Gabriel Silberman, IBM Research
Panelists: Kemal Ebcioglu, Yale N. Patt, Richard Wirt
3.2.4: Future Asynchronous Designs, Chair: Larry Pileggi, Carnegie Mellon University
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RSFQ: What We Know and What We Don't
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Efficient Delay-Insensitive RSFQ Circuits
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Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum
Devices
3.3.1: Sequential Synthesis, Chair: Lukas van Ginneken, Synopsis, Inc.
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Exact Dichotomy-based Constrained Encodin
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Latch Redundancy Removal Without Global Reset
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A Practical Algorithm for Retiming Level-Clocked
Circuits
3.3.2: Integration Support, Chair: Gabriel Bischoff, DAC
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Distributed EDA Tool Integration: The PPP Paradigm
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A
Method for Analog Circuits Visualization
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Cycle-Based Timing Simulations Using Event-Streams
3.3.3: Special Session
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Performance Analysis and Validation
Chair: Pradip Bose, IBM Research
Organizers: Tom Conte, North Carolina State University; Ashiwini Nanda, IBM Research -
Reducing State Loss For Effective Trace Sampling of
Superscalar Processors
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Can Trace-Driven Simulators Accurately Predict
Superscalar Performance?
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The Augmint multiprocessor simulation toolkit for
Intel x86 architectures
3.3.4: VLSI Signal Processors, Chair: Jacob A. Abraham, University of Texas at Austin
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Systematic analysis of bounds on power consumption
in pipelined and non-pipelined multipliers
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A VLSI chip for image compression using variable
block size segmentation
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On Design of Efficient Square Generator
3.4.1: Architectural Issues in High Level Synthesis, Chair: Masahiro Fujita, Fujitsu Laboratories of America, Inc.
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Autocircuit: a clock edge general behavioral
synthesis system with a direct path to physical datapaths
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Synthesis of Multi-Dimensional Applications in VHDL
3.4.2: Arithmetic Circuits, Chair: N. Ranganathan, University of South Florida
3.4.3: Special Session: The Development of the AMD-K5 Architecture, Chair: Kimming So, AMD
3.4.4: Synthesis for FPGAs, Chair: Timothy Kam, Intel Corporation
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FPGA Module Minimization
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An Improved Algorithm for Performance Optimal Technology Mapping with
Retiming in LUT-Based FPGA Design
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Multiway Partitioner for High Performance FPGA Based
Board Architectures