Keynote Address
1.2.1: CAD Plenary
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A Brief History of the Future of Semiconductor
Electronic Design Automation
Chair: Andreas Kuehlmann, IBM T.J. Watson Research Center
Speaker: Ron Rohrer, TBD Consultants
1.3.1: Special Session: Industrial Applications of Formal Verification
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Formal implementation verification of the bus
interface unit for the Alpha 21264 microprocessor
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Intertwined development and formal verification of a
60/spl times/ bus model
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Formally specifying and mechanically verifying
programs for the Motorola complex arithmetic processor DSP
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BIST-based fault diagnosis in the presence of
embedded memories
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Built-In Self Test for Content Addressable Memories
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Pseudo-random pattern testing of bridging faults
1.3.3: Simulation and Power Estimation
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Novel Simulation of Deep-Submicron MOSFET Circuits
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Time-stamped transition density for the estimation
of delay dependent switching activities
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Power compiler: a gate-level power optimization and
synthesis system
1.3.4: Branch Prediction
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Elastic History Buffer: A Low-Cost Method to Improve
Branch Prediction Accuracy
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Design optimization for high-speed per-address
two-level branch predictors
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PA-8000: a case study of static and dynamic branch
prediction
1.4.1: New Techniques for Gate-Sizing and Retiming
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Discrete drive selection for continuous sizing
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Continuous retiming: algorithms and applications
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Optimal clock period clustering for sequential
circuits with retiming
1.4.2: Circuit Modeling
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Comparison between nMOS pass transistor logic style
vs. CMOS complementary cells
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Circuit-based description and modeling of
electromagnetic noise effects in packaged low-power electronics
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Transistor-Level Sizing and Timing Verification of
Domino Circuits in the Power PC(TM) Microprocessor
1.4.3: Novel Architectures
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Architectural adaptation for application-specific
locality optimizations
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A New Processor Architecture for Digital Signal
Transport Systems
Short Papers
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PROPHID: a heterogeneous multi-processor
architecture for multimedia
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Enhanced compression techniques to simplify program
decompression and execution
1.4.4: Low Power Architectures
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A
low power approach to floating point adder design
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Design and implementation of low-power digit-serial
multipliers
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On complexity reduction of FIR digital filters using
constrained least squares solution
1.5.1: Timing Optimization for Deep Submicron Technology
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An integrated placement and synthesis approach for
timing closure of PowerPC/sup TM/ microprocessors
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Post-layout circuit speed-up by event elimination
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Clustering and load balancing for buffered clock
tree synthesis
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CMOS gate delay models for general RLC loading
1.5.2: Special Session: The G4 S/390 Microprocessor
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Design methodology for the high-performance G4 S/390 microprocessor
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A high-frequency custom CMOS S/390 microprocessor
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High performance CMOS circuit techniques for the G-4
S/390 microprocessor
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A 400MHz, 144Kb CMOS ROM Macro for an IBM
S/390-Class Microprocessor
1.5.3: Multiprocessor Communication
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A comparative evaluation of hierarchical network
architecture of the HP-Convex Exemplar
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Effect of message length and processor speed on the
performance of the bidirectional ring-based multiprocessor
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An approach to network caching for multimedia
objects
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Development of a High Bandwidth Merged Logic/DRAM
Multimedia Chip
1.5.4: Asynchronous Architectures
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TITAC-2: an asynchronous 32-bit microprocessor based
on scalable-delay-insensitive model
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An Evaluation of Asynchronous and Synchronous Design
for Superscalar Architectures
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Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
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Asynchronous Wrapper for Heterogeneous Systems
1.6.1:
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The War of the Roses: Designers Versus Tool
Developers
Organizer: Andreas Kuehlmann, IBM, T.J. Watson Research Center
Moderator: Daniel Beece, IBM T.J. Watson Research Center
Panelists: Barbara Chappell, Intel Corp.; Robert Damiano, Synopsys, Inc.; Charlie Malley, Hewlett-Packard; Yiannos Manoli, University of Saarland; David F. Reed, AMD; Steven E. Schulz, Texas Instruments
1.6.2:
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If Software is King for Systems-on-Silicon, What's
New in Compilers?
Organizer: Nikil Dutt, University of California at Irvine
Moderator: Sharad Malik, Princeton University
Panelists: Lex Augusteijn, Philips Research Laboratory; Beatrice Fu, Intel Corporation, Alex Nicolau, University of California at Irvine; Constantine Polychronopoulos, University of Illinois at Urbana-Champaign
2.1.1: Design and Test Plenary
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Design and test: The Lost World
Chair: Magdy Abadir, Motorola, Inc.
Speaker: W. Joyner, IBM T.J. Watson Research Center
2.2.1: Binary Decision Diagrams
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Equivalence checking using abstract BDDs
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Speeding up variable reordering of OBDDs
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Dynamic reordering in a breadth-first manipulation
based BDD package: challenges and solutions
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Timed binary decision diagrams
2.2.2: Advanced Test Topics
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Vector restoration based static compaction of test
sequences for synchronous sequential circuits
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Nonenumerative path delay fault coverage estimation
with optimal algorithms
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Properties of the input pattern fault model
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A new approach for initialization sequences
computation for synchronous sequential circuits
2.2.3: Embedded Software and Systems
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Real-Time Operating Systems for Embedded Computing
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Allocation and Data Arrival Design of Hard Real-time
Systems
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Improving design turnaround time via two-levels
HW/SW co-simulation
2.2.4: Low Power Issues
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Power constrained design of multiprocessor
interconnection networks
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Memory traffic and data cache behavior of an MPEG-2
software decoder
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Asynchronous transpose-matrix architectures
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A low power smart vision system based on active
pixel sensor integrated with programmable neural processor
2.3.1: Formal Verification Methods
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Formal verification of the HAL S1 System cache
coherence protocol
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A Survey of Techniques for Formal Verification of
Combinational Circuits
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Checking formal specifications under simulation
2.3.2: Mixed Signal Design and Test
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Built-In Temperature Sensors for On-line Thermal
Monitoring of Microelectronic Structures
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Development of hierarchical testability design
methodologies for analog/mixed-signal integrated circuits
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A novel test set design for parametric testing of
analog and mixed-signal circuits
2.3.3: FPGA Design
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On the Construction of Universal Series-Parallel
Functions for Logic Module Design
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A universal Pezaris array multiplier generator for
SRAM-based FPGAs
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Channel Segmentation Design for Symmetrical FPGAs
2.3.4: Cache Technology I
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Multi-column implementations for cache associativity
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Design and performance evaluation of a cache assist
to implement selective caching
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On effective data supply for multi-issue processors
2.4.1: Embedded Tutorial
2.4.2: Fault Diagnosis
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First test results of system level fault tolerant
design validation through laser fault injection
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Integrated Diagnostics for Embedded Memory Built-in
Self Test on PowerPCTM Devices
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A TSC evaluation function for combinational circuits
2.4.3: Special Session: Low Power Design Issues
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An architectural power optimization case study using
high-level synthesis
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High-Level Design Synthesis of a Low Power, VLIW
Processor for the IS-54 VSELP Speech Encoder
2.4.4: Cache Technology II
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Fast cache access with full-map block directory
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A data alignment technique for improving cache
performance
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Instruction prefetching using branch prediction
information
3.1.1: Architecture & Algorithm Plenary
3.2.1: Layout Partitioning and Synthesis
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An efficient multi-way algorithm for balanced
partitioning of VLSI circuits
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Partitioning under timing and area constraints
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A parallel circuit-partitioned algorithm for timing
driven cell placement
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Crosstalk-Constrained Maze Routing Based on
Lagrangian Relaxation
3.2.2: Design for Testability & Test Synthesis
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High level test synthesis across the boundary of
behavioral and structural domains
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Power driven partial scan
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Synthesis of delay verifiable sequential circuits
using partial enhanced scan
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Application of a testing framework to VHDL
descriptions at different abstraction levels
3.2.3: Embedded Tutorial
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Practical advances in asynchronous design
Chair: Rob Roy, NEC, Inc.
Presenters: Eric Brunvand of The University of Utah, Steve Nowick of Columbia University, Kenneth Yun of The University of California at San Diego
3.2.4: Arithmetics
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Benchmarking and analysis of architectures for CAD
applications
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Fast Low-Energy VLSI Binary Addition
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A floating-point divider using redundant binary
circuits and an asynchronous clock scheme
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Parallel-array implementations of a non-restoring
square root algorithm
3.3.1: Asynchronous Design
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Optimizing CMOS Implementations of the C-element
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A doubly-latched asynchronous pipeline
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A pulse-to-static conversion latch with a self-timed
control circuit
3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies
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Fast Generation of Statistically-based Worst-Case
Modeling of On-Chip Interconnect
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A repeater optimization methodology for deep
sub-micron, high-performance processors
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Critical voltage transition logic: an ultrafast CMOS
logic family
3.3.3: Finite-State Machine and High-Level Synthesis
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Divide & Conquer: A Strategy for Synthesis of Low
Power Finite State Machines
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Estimation of maximum power for sequential circuits
considering spurious transitions
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Dynamic bounding of successor force computations in
the force directed list scheduling algorithm