Keynote Address
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Deep Blue: The IBM Chess Machine
Murray S. Campbell, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
1.2: Plenary
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Making Computer-Dependent Airplanes Safer through Formal Methods
Organizer and Chair: Warren A. Hunt, Jr., IBM Austin Research Center, TX, USA
Speaker: Ricky W. Butler
1.3.1: Special Invited Session: A Prototype 1 GHz PowerPC Microprocessor
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A 690ps Read-Access Latency Register File for a GHz
Integer Microprocessor
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Circuit Design Techniques for a Gigahertz Integer
Microprocessor
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Design Methodology for a 1.0 GHz Microprocessor
1.3.2: Built-in-Self-Test
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Improved Built-In Test Pattern Generators Based on
Comparison Units for Synchronous Sequential Circuits
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Efficient BIST TPG Design and Test Set Compaction
for Delay Testing via Input Reduction
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Testing Digital to Analog Converters based on
Oscillation-Test Strategy using Sigma-delta Modulation
1.3.3: Design Optimization
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System-Level Performance Estimation Strategy for Sw
and Hw
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Accuracy Sensitive Word--Length Selection for
Algorithm Optimization
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Optimal design of synchronous circuits using
software pipelining techniques
1.3.4: Power and Noise Estimation and Optimization
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On Short Circuit Power Estimation of CMOS Inverters
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Methods for Calculating Coupling Noise in Early
Design: A Comparative Analysis
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Low Power SRAM Design using Hierarchical Divided
Bit-Line Approach
Lunch Presentation
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The Transformation of the IBM S/390 Enterprise Servers
Speaker: Gururaj Rao, IBM Corp., Poughkeepsie, NY, USA
1.4.1: Special Invited Session: The Alpha 21264 Microprocessor
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The Alpha 21264 Microprocessor Architecture
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Timing Verification of the 21264: A 600MHz
Full-Custom Microprocessor
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Circuit Implementation of a 600MHz Superscalar RISC
Microprocessor
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Zen and the Art of Alpha Verification
1.4.2: Technical Forum
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Technology Challenges for Design and Computer-Aided Design of Digital
Integrated Circuits
Organizer: Joel Grodstein, Digital Equipment Corporation, Palo Alto, CA, USA
Moderator: Kenneth L. Shepard, Columbia University, New York, NY, USA
Speakers: Shantanu Ganguly, Lisa Su, Chris Ang, Andrew Kahng, Ray Stephany
1.4.3: Arithmetic I
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A Reduction Scheme to Optimize the Wallace
Multiplier
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Fast Low-Power Shared Division and Square-Root
Architecture
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Area Minimization of Redundant CORDIC Pipeline
Architectures
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How Many Logic Levels Does Floating-Point Addition
Require?
1.4.4: Logic Synthesis
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Efficient Exact and Heuristic Minimization of
Hazard-Free Logic
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Area-Oriented Synthesis for Pass-Transistor Logic
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New Compact Representation of Multiple-Valued
Functions, Relations, and Non-deterministic State Machines
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A Low-Power Logic Optimization Methodology based on
a Fast Power-Driven Mapping
1.5 Poster Session
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A Fine-Grain, Current Mode Scheme for VLSI Proximity
Search Engine
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An Effective Datapath Design Methodology for
High-Frequency Design
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Adaptive Synchronization
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The Microcore Development System ¾ A Unified
Environment for Designing New Microprocessors
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Automatic Data Path Abstraction for Verification of
Large Scale Designs
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Model Checking of a Real ATM Switch
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Performance-Driven Board-Level Routing for FPGA-based
Logic Emulation
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Re-synthesis in Technology Mapping for Heterogeneous
FPGAs
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A Simple Adaptive Wormhole Routing Algorithm for
MIMD Systems
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Branch Assertion and Elimination
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High-Performance Digit-Serial Complex-Number
Multiplier-Accumulator
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Dynamic Fault Diagnosis for Sequential Circuits on
Reconfigurable Hardware
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On Thin Boolean Functions and Related Optimal OBDD
Ordering
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Clock-Skew Constrained Placement for Row Based
Designs
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Antirandom vs. Psuedorandom Testing
1.6.1: Panel
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Formal Verification ¾ "Peripheral" or "Indispensable"?
Organizer and Moderator: Andreas Kuehlmann, IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Panelists: Dennis Abts, David L. Dill, Asgeir P. Eiríksson, Kenneth L. McMillan, Robert P. Kurshan
2.1: Plenary
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Architects Should not Write Checks that Design Teams Can't Cash
2.2.1: Special Invited Session: The ARM Microprocessor
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The ARM9 Family - High Performance Microprocessors
for Embedded Applications
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The System Design of a Windows CE ARM based
Micro-controller
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Hardware/Software Co-verification, an IP Vendors
Viewpoint
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AMULET3: A High-Performance Self-Timed ARM
Microprocessor
2.2.2: Technical Forum
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Dynamically and Partially Reconfigurable Architectures: New
Opportunities and Challenges
Organizer and Moderator: Sarma Vrudhula, University of Arizona, Tucson, AZ, USA
Speakers: Sarma Vrudhula, Ranga Vemuri, Viktor K. Prasanna, Peter Athanas, Olgierd Palusinski, Sanjaya Kumar
2.2.3: Embedded Tutorial
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Noise and Signal Integrity Issues in Deep Submicron Design
Organizer and Chair: Sandip Kundu, Intel Corp., Santa Clara, CA, USA
Speaker: Anirudh Devgan, IBM Austin Research Laboratory, TX, USA
2.2.4: High Performance Design Techniques
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Deep Submicron Design Techniques for the 500MHz IBM
S/390 G5 Custom Microprocessor
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Comparative Analysis of Latches and Flip-Flops for
High-Performance Systems
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Design Issues in Mixed Static-Domino Circuit
Implementations
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A Fast Global Gate Collapsing Technique for High
Performance Designs using Static CMOS and Pass Transistor Logic
Lunch Presentation
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AltiVec: Motorola's High Performance Vector Parallel Processing
Expansion to the PowerPC Architecture
Speaker: Michael Phillip, Motorola Inc., Austin, TX, USA
2.3.1: Arithmetic II
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A Minimized Hardware Architecture of Fast Phong
Shader Using Taylor Series Approximation in 3D Graphics
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Pipelined Computation of LNS Addition/Subtraction
with Very Small Lookup Tables
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Leading-One Prediction Scheme for Latency
Improvement in Single Datapath Floating--Point Adders
2.3.2: Practical Functional Verification
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An Approach to Verify a Large Scale System-on-a-chip
Using Symbolic Model Checking
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To Model Check Or Not To Model Check
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VEGA: A Verification Tool Based on Genetic
Algorithms
2.3.3: System Performance Issues
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Software Power Estimation and Optimization for High
Performance, 32-bit Embedded Processors
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FPGA-Based Internet Protocol Version 6 Router
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Partitioning in Time : A Paradigm for Reconfigurable
Computing
2.3.4: Asynchronous Design Techniques
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Pulse-Mode Macromodular Systems
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Practical Design and Performance Evaluation of
Completion Detection Circuits
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Rapid Prototyping of Self-timed Circuits
2.4.1: Cache and Memory Systems
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Evaluating the Performance of Active Cache
Management Schemes
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Data Cache Parameter Measurements
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Fault-Tolerant Architecture for High Performance
Embedded System Applications
2.4.2: Timing and Synthesis Verification
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Theorem Proving Guided Development of Formal
Assertions in a Resource-Constrained Scheduler for High-Level Synthesis
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Incorporating Timing Constraints in the Efficient
Memory Model for Symbolic Ternary Simulation
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Timing Analysis of Combinational Circuits Containing Complex Gates
2.4.3: Low Power/High Efficiency Networks
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Extension of the Working-Zone-Encoding Method to Reduce the Energy on
the Microprocessor Data Bus
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Low-Power Radix-8 Divider
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A Self-Timed Real-Time Sorting Network
2.4.4: High-Level Synthesis
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Automatic VHDL Restructuring for RTL Synthesis
Optimization and Testability Improvement
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DCP: an Algorithm for Datapath/Control Partitioning
of Synthesizable RTL Models
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Hierarchical Pipelining for Behaviors, Loops and
Operations
2.5.1: Panel
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Legacy Instruction Sets: Aging Like Fine Wine, or Rusting Like Old
Buicks?
Organizers: Craig M. Chase, The University of Texas at Austin, USA and David Witt, AMD, Austin, TX, USA
Moderator: Andrew Pleszkun, University of Colorado, Boulder, CO, USA
Panelists: Glenn J. Hinton, G. Glenn Henry, Mark Dean, Dave Christie
Dinner Presentation
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Venture Capital and the Start-up Company
James H. Clardy, Venture Partner at Austin Ventures, Austin, TX, USA
3.1: Plenary
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The Unbundling of the Semiconductor Industry
Organizer and Chair: Kenneth L. Shepard, Columbia University, New York, NY, USA
Speaker: Lucio Lanza
3.2.1: Embedded Tutorial
3.2.2: VLIW and Parallel Processing
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Circular Buffered Switch Design with Wormhole
Routing and Virtual Channels
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The Effects of Explicitly Parallel Mechanisms on the
Multi-ALU Processor Cluster Pipeline
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Parallel Ultra Large Scale Engine SIMD Architecture
For Real-Time Digital Signal Processing Applications
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An Eight Issue Tree-VLIW Processor for Dynamic
Binary Translation
3.2.3: ATPG
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On Finding Undetectable and Redundant Faults in
Synchronous Sequential Circuits
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Enhancing Topological ATPG with High-Level
Information and Symbolic Techniques
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An Exact Solution to the Minimum Size Test Pattern
Problem
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Using Regression Analysis for GA-Based ATPG
Parameter Optimization
3.2.4: Timing and Power Analysis
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Static Race Verification for Networks with
Reconvergent Clocks
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Finding The Longest Simple Path in Cyclic
Combinational Circuits
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Practical Use of Transition Mode Delay to Solve the
Problems of Floating Mode Delay under Highly Correlated Input Streams
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A
Fractal Compaction Algorithm for Efficient Power Estimation
3.3.1: Performance Analysis and Microarchitecture
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Code Coalescing Unit: A Mechanism to Facilitate Load
Store Data Communication
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Profiling for Input Predictable Threads
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Analysis of x86 Instruction Set Usage for
DOS/Windows Applications and Its Implication on Superscalar Design
3.3.2: Mixed Signal Testing
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Current-Based Testing for Analog and Mixed-Signal
Circuits
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Test Points Selection Process and Diagnosability
Analysis of Analog Integrated Circuits
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Fault Detection and Automated Fault Diagnosis for
Embedded Integrated Electrical Passives
3.3.3: Co-Design
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Buffer Size Driven Partitioning for HW/SW Co-Design
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Scheduling Under Data and Control Dependencies for
Heterogeneous Architectures
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Integrated Partitioning and Scheduling for Hardware/Software Co-design
3.3.4: Place and Route
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Combining Technology Mapping with Post-Placement
Resynthesis for Performance Optimization
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Learning as Applied to Stochastic Optimization for
Standard Cell Placement
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Timing-Driven Routing for Symmetrical-Array-Based
FPGAs