Keynote Speaker
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On the Road to a Mobile Information Society
Dirk Friebel, Nokia GmbH-Nokia Research Center
1.1 New Architectures, Chair: Mauricio Breternitz, Motorola
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Architectural Impact of Secure Socket Layer on Internet Servers
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Fast Subword Permutation Instructions Using Omega and Flip Network
Stages
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Sleipnir-An Instruction-Level Simulator Generator
1.2 Fault-Simulation and ATPG at Different Design Levels, Chair: Nur Touba, The University of Texas at Austin
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Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping
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Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
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An Application of Genetic Algorithms and BDDs to Functional Testing
1.3 Advanced Design Techniques, Chair: Ken Shepard, Columbia University
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High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM)
Technology
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Estimation of Inductive and Resistive Switching Noise on Power Supply
Network in Deep Sub-Micron CMOS Circuits
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Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous
Systems
2.1 Improving CPU Performance, Chair: Brian Grayson, Motorola
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Hybridizing and Coalescing Load Value Predictors
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A
2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache
Scheme for Object-Oriented Languages
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Architectural Support for Dynamic Memory Management
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SCIMA: Software Controlled Integrated Memory Architecture for High
Performance Computing
2.2 Parasitic Modeling, Analysis, and Optimization, Chair: Tom Dillinger, Sun Microsystems
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Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
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Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
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An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using
Microstrip Lines Theory
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Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction
on Distributed Memory Multiprocessors
2.3 Low Power and Arithmetic, Chair: Margarida Jacome, The University of Texas at Austin
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A
Novel Low-Power Microprocessor Architecture
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A
Power Perspective of Value Speculation for Superscalar Microprocessors
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Multilevel Reverse-Carry Adder
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Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW
and Superscalar Architectures
3.1 Servers and Parallelism, Chair: Ruby Lee, Princeton University
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Unified Fine-Granularity Buffering of Index and Data: Approach and
Implementation
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Analysis of Shared Memory Misses and Reference Patterns
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Power-Sensitive Multithreaded Architecture
3.2 Circuit Optimization and Analysis, Chair: Shervin Hojat, IBM
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Delay Constrained Optimization by Simultaneous Fanout Tree Construction,
Buffer Insertion/Sizing and Gate Sizing
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Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz
PowerPC(tm) Microprocessor
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Buffer Library Selection
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High-Performance Low-Power CMOS Circuits Using Multiple Channel Length
and Multiple Oxide Thickness
3.3 Logic Circuit Families, Chair: Shyh-Jye Jou, National Central University
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Current-Mode Threshold Logic Gates
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Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit
Family
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Output Prediction Logic: A High-Performance CMOS Design Technique
Keynote Address
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The Future of Populist Parallelism
Greg Pfister, IBM Advanced Technology & Architecture, Server Design
4.1 Intelligent Memory, Chair: Steven Reinhardt, University of Michigan
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A
Study of Channeled DRAM Memory Architectures
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DRAM-Page Based Prediction and Prefetching
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Reducing Cost and Tolerating Defects in Page-based Intelligent Memory
4.2 Processor Microarchitecture, Chair: Steve Furber, The University of Manchester
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A
Selective Temporal and Aggressive Spatial Cache System Based on Time
Interval
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Design of Instruction Stream Buffer with Trace Support for X86
Processors
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A
Trace Based Evaluation of Speculative Branch Decoupling
4.3 Digital Logic Techniques, Chair: Barbara Chappell, Accelerant Networks
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An Adder Using Charge Sharing and its Application in DRAMs
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Fixed-Width Multiplier for DSP Application
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Dynamic Flip-Flop with Improved Power
5.1: Embedded Processors: Architecture and System-Design Issues, Chair: Ricardo Gonzales, Tensilica
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Processors for Mobile Applications
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AMULET3: A 100 MIPS Asynchronous Embedded Processor
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Xtensa with User Defined DSP Coprocessor Microarchitectures
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Predictive Strategies for Low-Power RTOS Scheduling
5.2: Floorplanning and Partitioning, Chair: Tim Burks, Magma Design Automation
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Rectilinear Block Placement Using B*-Trees
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Fast Hierarchical Floorplanning with Congestion and Timing Control
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An Evaluation of Move-Based Multi-Way Partitioning Algorithms
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Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan
Synthesis
5.3: Basic Algorithms in Verification and Test, Chair: Yatin Hoskote, Intel
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On Solving Stack-Based Incremental Satisfiability Problems
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Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound
Computation
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Sensitivity Levels of Test Patterns and Their Usefulness in
Simulation-Based Test Generation
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On Test Application Time and Defect Detection Capabilities of Test Sets
for Scan Designs
6.1: Special Session: Advancements in DSP
Architecture
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Effective Hardware-Based Two-Way Loop Cache for High Performance Low
Power Processors
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A
Multi-Level Memory System Architecture for High-Performance DSP
Applications
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A
Scalable High-Performance DMA Architecture for DSP Applications
6.2: Advanced Architectural Design and Synthesis, Chair: Edward Grochowski, Intel
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Efficient Place and Route for Pipeline Reconfigurable Architectures
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PEAS-III: An ASIP Design Environment
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Symbolic Binding for Clustered VLIW ASIPs
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Interfacing Hardware and Software Using C++ Class Libraries
6.3: Application and Case Studies in Test and Verification, Chair: Carl Pixley, Motorola
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Formal Verification of an Industrial System-on-a-Chip
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Equivalence Checking Combining a Structural SAT-Solver, BDDs, and
Simulation
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Efficient Design Error Correction of Digital Circuits
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An Automatic Validation Methodology for Logic BIST in High Performance
VLSI Design
Invited Paper
7.1: Logic Optimization, Chair: Chin-Long Wey, Michigan State University
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Efficient Logic Optimization Using Regularity Extraction
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Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
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Minimization of Ordered Pseudo Kronecker Decision Diagrams
7.2: High Level Specification and Synthesis, Chair: Pranav Ashar, NEC
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Rethinking Behavioral Synthesis for a Better Integration within Existing
Design Flows
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Synthesis and Optimization of Interface Hardware between IP's Operating
at Different Clock Frequencies
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Multi-Level Communication Synthesis of Heterogeneous Multilanguage
Specification
Poster Sessions
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Low Power Video Object Motion-Tracking Architecture
for Very Low Bit Rate Online Video Applications
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An SEU Injection Tool to Evaluate DSP-Based
Architectures for Space Applications
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On Integrating a Proprietary and a Commercial
Architecture for Optimal BIST Performances in SoCs
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Static Timing Analysis with False Paths
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A
Methodology and Tool for Automated Transformational High-Level Design
Space Exploration
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Cheap Out-of-Order Execution Using Delayed Issue
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Representing and Scheduling Looping Behavior Symbolically
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Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz
Era and Beyond
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A
Register File with Transposed Access Mode
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Leakage Power Analysis and Reduction during Behavioral Synthesis
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An Advanced Instruction Folding Mechanism for a Stackless Java Processor
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OpenDesign: An Open User-Configurable Project Environment for
Collaborative Design and Execution on the Internet
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A
Decompression Architecture for Low Power Embedded Systems
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Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context
Reconfigurable Architectures
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The M˙CORE(TM) M340 Unified Cache Architecture
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Crosstalk-Constrained Performance Optimization by Using Wire Sizing and
Perturbation
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Hierarchical Simulation of a Multiprocessor Architecture
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Multiple Precision Based Montgomery Multiplication without
Precomputation of N0´ = -N0-1 mod W
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A
Technique for Identifying RTL and Gate-Level Correspondences
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A
Direct Mapping FPGA Architecture for Industrial Process Control
Applications
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Source-Level Transformations for Improved Formal Verification