Keynote Speakers
-
The In-Car Computing Network: A Challenge for Embedded Systems
-
Clear and Present Tensions in Microprocessor Design
-
Moore's Law Meets Shannon's Law: The Evolution of the Communications
Industry
1.1: Asynchronous Techniques
-
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
-
Arithmetic Logic Circuits using Self-Timed Bit Level Dataflow and Early
Evaluation
-
Efficient Systematic Error-Correcting Codes for Semi-Delay-Insensitive
Data Transmission
1.2: Embedded Tutorial
-
Design Constraints for Efficient Cryptographic Processing in Smart Cards
Jean-François Dhem -
Security of Smartcard Integrated Circuits
1.3: Architectural Modeling: Performance and Power Analysis
-
Minimal Subset Evaluation : Rapid Warm-Up for Simulated Hardware State
-
A
Framework for Energy Estimation of VLIW Architecture
-
High-Level Power Modeling of CPLDs and FPGAs
2.1: Caching
-
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation
of Loads and Stores
-
In-Line Interrupt Handling for Software-Managed TLBs
-
Design of a Predictive Filter Cache for Energy Savings in High
Performance Processor Architectures
2.2: Simulation Based Verification
-
A
New Functional Test Program Generation Methodology
-
A
Functional Validation Technique: Biased-Random Simulation Guided by
Observability-Based Coverage
-
Selecting a Well Distributed Hard Case Test Suite for IEEE Standard
Floating Point Division
2.3: Modeling of Capacitance and Crosstalk Noise
-
Linear Time Hierarchical Capacitance Extraction without Multipole
Expansion
-
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI
Circuits
-
Crosstalk Noise Estimation for Generic RC Trees
3.1: Improving the Performance of Caching Structures
-
A Banked-Promotion TLB for High Performance and Low
Power
-
Filtering Superfluous Prefetches Using Density Vectors
-
Allocation by Conflict: A Simple, Effective Multilateral Cache
Management Scheme
3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
-
COREL: A Dynamic Compaction Procedure for Synchronous Sequential
Circuits with Repetition and Local Static Compaction
-
A
Partitioning and Storage Based Built-In Test Pattern Generation Method
for Synchronous Sequential Circuits
-
Cost-Effective Non-Scan Design for Testability for Actual Testability
Improvement
3.3: Invited Session: Power 4 Microprocessor- Organizer: J. M. Tendler
-
Power4 Microprocessor
and System Design
Joachim Clabes, IBM Austin -
Power4 Design
Methodology
Brian Zoric, IBM Austin -
Semi-Custom Design
Methodology for Power4
Philip Strenski, IBM Yorktown -
Power4 Integration
Michael Scheuermann, IBM Yorktown
4.1: Embedded Tutorial
4.2: Computer Arithmetic
-
Improved ZDN-Arithmetic for Fast Modulo Multiplication
-
Design Alternatives for Parallel Saturating Multioperand Adders
-
A
Single-Multiplier Quadratic Interpolator for LNS Arithmetic
4.3: Circuit Sizing and Optimization
-
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
-
Performance Optimization by Wire and Buffer Sizing under the
Transmission Line Model
- Buffered Interconnect Tree Optimization using Lagrangian Relaxation and Dynamic Programming
5.1: Clocking and Time-Domain Measurements
-
Embedded Tutorial: Clocked Timing Elements for High-Performance and
Low-Power VLSI Systems
- Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective
-
On the Micro-Architectural Impact of Clock Distribution Using Multiple
PLLs
-
On-Chip Oscilloscopes for Noninvasive Time-Domain Measurement of
Waveforms
5.2: Processor Microarchitecture
-
Selective Branch Prediction Reversal by Correlating with Data Values and
Control Flow
-
Mutable Functional Units and Their Applications on Microprocessors
-
Compiler-Directed Classification of Value Locality Behavior
-
A
Hierarchical Dependence Check and Folded Rename Mapping Based Scalable
Dispatch Stage
5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
-
Designing Circuits for Disk Drives
-
Hard Disk Controller: The Disk Drive's Brain and Body
-
Motion-Control: The Power Side of Disk Drives
6.1: Energy Efficiency Caches and Multiport Cache Structures
-
Static Energy Reduction Techniques for Microprocessor Caches
-
Parallel Cachelets
-
Access Region Cache: A Multi-Porting Solution for Future Wide-Issue
Processors
6.2: Control by Simulation and On-line Checking
-
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits
-
High Performance Parallel Fault Simulation
-
On-Line Integrity Monitoring of Microprocessor Control Logic
6.3: CAD Algorithms for Physical Design
-
A
Timing-Driven Macro-Cell Placement Algorithm
-
Fixed-Outline Floorplanning through Better Local Search
-
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA
Partitioning
Panel Discussion
7.1: Invited Session: Network Processors
- Session Abstract
-
Network Processing: Applications and Challenges
-
Payload+: Fast Pattern Matching and Routing for OC-48
-
Scaling Fully Programmable Network Processing to 10Gbps and Beyond
7.2: Formal Methods for Property Verification and Equivalence Verification
-
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths
-
Hierarchical Image Computation with Dynamic Conjunction Scheduling
-
Introduction to Generalized Symbolic Trajectory Evaluation
7.3: Hardware Representation
-
BDD Variable Ordering by Scatter Search
-
Lower Bound Based DDD Minimization for Efficient Symbolic Circuit
Analysis
-
Run-Time Execution of Reconfigurable Hardware in a Java Environment
8.1: Circuit Techniques
-
Realization of Multiple-Output Functions by Reconfigurable Cascades
-
A
Low-Power Cache Design for CalmRISC(tm)-Based Systems
-
Interconnect-Centric Array Architectures for Minimum SRAM Access Time
-
Understanding and Addressing the Noise Induced by Electrostatic
Discharge in Multiple Power Supply Systems
8.2: DSP/Multimedia
-
Cost-Effective Hardware Acceleration of Multimedia Applications
-
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented
TriMedia Processor
-
Low-Energy DSP Code Generation Using a Genetic Algorithm
-
Voltage Scaling for Energy Minimization with QoS Constraints
8.3: Novel Architectures and ISA Extensions
-
Matching Architecture to Application via Configurable Processors: A Case
Study with Boolean Satisfiability Problem
-
Architectural Enhancements for Fast Subword Permutations with
Repetitions in Cryptographic Applications
-
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image
Synthesis
-
Use of Local Memory for Efficient Java Execution
Poster Papers
-
An Analytical Model for Trace Cache Instruction Fetch Performance
-
Performance Driven Global Routing through Gradual Refinement
-
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI
Placement
-
Fast Specification of Cycle-Accurate Processor Models
-
A
Performance Analysis of the Active Memory System
-
Combined IEEE Compliant and Truncated Floating Point Multipliers for
Reduced Power Dissipation
-
An Algorithm for Dynamically Reconfigurable FPGA Placement
-
RC-In RC-Out Model Order Reduction Accurate up to Second Order Moments
-
Efficient Function Approximation for Embedded and ASIC Applications
-
An Area-Efficient Iterative Modified-Booth Multiplier Based on
Self-Timed Clocking
-
A
Heuristic for Multiple Weight Set Generation
-
Towards a Formal Model of Shared Memory Consistency for Intel Itanium(tm)
-
Efficient Algorithms for Subcircuit Enumeration and Classification for
the Module Identification Problem
-
MCOMA: A Multithreaded COMA Architecture
-
Automatic Generation and Validation of Memory Test Models for High
Performance Microprocessors
-
Reducing Cache Pollution of Prefetching in a Small Data Cache
-
Alloyed Path-Pattern Scheme for Branch Prediction
-
Timing Characterization of Dual-Edge Triggered Flip-Flops
-
Performance Impact of Addressing Modes on Encryption Algorithms
-
Determining Schedules for Reducing Power Consumption Using Multiple
Supply Voltages
-
Pre-Routing Estimation of Shielding for RLC Signal Integrity