Keynote Speakers
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Supercomputing on a Chip: Evolution and Challenges
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From IP
to Platforms
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Application
Specific Embedded Processors for Next Generation Communication Systems
1.1: Special Invited Session: Computers in Media, Mobile and Servers
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Design Methodology and System for a Configurable Media Embedded
Processor Extensible to VLIW Architecture
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Low Power Design Methodologies for Mobile Communication
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Power-Constrained Microprocessor Design
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Functional Verification of the IBM zSeries eServer z900 System
1.2: Physical Design
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A
CAD Tool for System-on-Chip Placement and Routing with Free-Space
Optical Interconnect
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Physical Planning Of On-Chip Interconnect Architectures
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An Efficient External-Memory Implementation of Region Query with
Application to Area Routing
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GPE: A New Representation for VLSI Floorplan Problem
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A
Standard-Cell Placement Tool for Designs with High Row Utilization
1.3: Verification
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k-time Forced Simulation: A Formal Verification Technique for IP Reuse
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Checking Equivalence for Circuits Containing Incompletely Specified
Boxes
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Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input
Ordering
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Environment Synthesis for Compositional Model Checking
2.1: Special Invited Session: Design ITRS 2001 — Issues and Solutions
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Physical Design Challenges for Billion Transistor Chips
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From ASIC to ASIP: The Next Design Discontinuity
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High Level Functional Verification Closure
2.2: Data Path Elements for Multi-GHz Design
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A
10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
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Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier
for Image Processing
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A
New Architecture for Signed Radix-2m Pure Array Multipliers
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A
Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators
for High-Performance Microprocessors
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Analysis of Blocking Dynamic Circuits
2.3: Multimedia and Arithmetic
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Parallel Multiple-Symbol Variable-Length Decoding
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Analysis of the Tradeoffs for the Implementation of a High-Radix
Logarithm
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Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable
Functional Caches (RFCs)
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Floating-Point Fused Multiply-Add with Reduced Latency
3.1: Methodology Issues for High Performance Designs
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Methodologies and Tools for Pipelined On-Chip Interconnect
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Timing Window Applications in UltraSPARC-IIIi™ Microprocessor Design
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A
System-Level Solution to Domino Synthesis with 2 GHz Application
3.2: Low-Power Microarchitecture
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Power-Performance Trade-Offs for Energy-Efficient Architectures: A
Quantitative Study
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Balancing the Interconnect Topology for Arrays of Processors between
Cost and Power
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A
Low Energy Set-Associative I-Cache with Extended BTB
3.3: Design for Testability
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Don't-Care Identification on Specific Bits of Test Patterns
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An Extended Class of Sequential Circuits with Combinational Test
Generation Complexity
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On the Coverage of Delay Faults in Scan Designs with Multiple Scan
Chains
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A
Test Processor Concept for Systems-on-a-Chip
4.1: Special Invited Session: Sensor Networks: New Architecture and Synthesis Challenges
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Locating Tiny Sensors in Time and Space: A Case Study
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A
Distributed Computation Platform for Wireless Embedded Sensing
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System-Architectures for Sensor Networks Issues, Alternatives, and
Directions
4.2: Computer Systems Design and Applications I
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Subword Sorting with Versatile Permutation Instructions
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Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors
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Performance Enhancements to the Active Memory System
4.3: Analog Test and Dependability
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Cost-Effective Concurrent Test Hardware Design for Linear Analog
Circuits
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Accurate and Efficient Static Timing Analysis with Crosstalk
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On the Detectability of Parametric Faults in Analog Circuits
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Using Offline and Online BIST to Improve System Dependability — The TTPC-C
Example
5.1: Special Session: The Imagine Processor
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The Imagine Stream Processor
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VLSI Design and Verification of the Imagine Processor
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Media Processing Applications on the Imagine Stream Processor
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A
Stream Processor Development Platform
5.2: Low Power Circuit Techniques
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Low-Power, High-Speed CMOS VLSI Design
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Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power
Reduction
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On The Impact of Technology Scaling On Mixed PTL/Static Circuits
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Power Analysis of Bipartition and Dual-Encoding Architecture for
Pipelined Circuits
5.3: Cache Memories
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Cache Design for Eliminating the Address Translation Bottleneck and
Reducing the Tag Area Cost
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A
Framework for Data Prefetching Using Off-Line Training of Markovian
Predictors
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Trace Cache Performance Parameters
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Data Cache Design Considerations for the Itanium® 2 Processor
6.1: Special Invited Session: Processors in Automotive Systems
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Requirements for Automotive System Engineering Tools
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Automotive Virtual Integration Platforms: Why’s, What’s, and How’s
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Models of IP’s for Automotive Virtual Integration Platforms
6.2: Power Management and High Level Synthesis
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Impact of Scaling on the Effectiveness of Dynamic Power Reduction
Schemes
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Modeling Switching Activity Using Cascaded Bayesian Networks for
Correlated Input Streams
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Register Binding Based Power Management for High-level Synthesis of
Control-Flow Intensive Behaviors
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Accelerated SAT-based Scheduling of Control/Data Flow Graphs
6.3: Speculative and Packet Oriented Architectures
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Trace-Level Speculative Multithreaded Architecture
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Speculative Trace Scheduling in VLIW Processors
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Embedded
Protocol Processor for Fast and Efficient Packet Reception
7.1: Interconnect Modeling and Analysis
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Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
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Exact Closed Form Formula for Partial Mutual Inductances of On-Chip
Interconnects
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Efficient PEEC-Based Inductance Extraction Using Circuit-Aware
Techniques
7.2: Issues in Processor Architecture
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Applying Decay Strategies to Branch Predictors for Leakage Energy
Savings
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Dynamic Loop Caching Meets Preloaded Loop Caching — A Hybrid Approach
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TTA-C2, A Single Chip Communication Controller for the
Time-Triggered-Protocol
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Adaptive Pipeline Depth Control for Processor Power-Management
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Branch Predictor Prediction: A Power-Aware Branch Predictor for
High-Performance Processors
- Improving Processor Performance by Simplifying and Bypassing Trivial Computations
7.3: Low Power Test, Diagnosis
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A
Low Power Pseudo-Random BIST Technique
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Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual
LFSR Re-Seeding
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Fault Dictionary Size Reduction through Test Response Superposition
Session 8.1: System Design Issues
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Designing an Asynchronous Microcontroller Using Pipefitter
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Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
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A
Design Methodology for Application-Specific Real-Time Interfaces
8.2: Computer Systems Design and Applications II
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TAXI: Trace Analysis for X86 Interpretation
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Embedded Operating System Energy Analysis and Macro-Modeling
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SIMD Extension to VLIW Multicluster Processors for Embedded Applications
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JMA: The Java-Multithreading Architecture for Embedded Processors