ICCD PROCEEDINGS 2003, IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN



	Welcome Organizing Committee Program Committee Additional Reviewers Keynote Speakers High-Speed Link Design, Then and Now Mark Horowitz Terascale Computing and BlueGene William Pulleyblank Advanced EDA Tools for High-Performance Design Ted Vucurevich 1.1 Energy Efficiency Energy Efficient Asymmetrically Ported Register Files Aneesh Aggarwal, Manoj Franklin Power Efficient Data Cache Designs Jaume Abella, Antonio González On Reducing Register Pressure and Energy in Multiple-Banked Register Files Jaume Abella, Antonio González Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition Masayuki Ito, David Chinnery, Kurt Keutzer 1.2 Timing Verification Verification of Timed Circuits with Failure Directed Abstractions Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits Gang Chen, Sudhakar M. Reddy, Irith Pomeranz Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits Marong Phadoongsidhi, Kewal K. Saluja Specifying and Verifying Systems with Multiple Clocks Edmund M. Clarke, Daniel Kroening, Karen Yorav 1.3 Electrical Analysis for System LSI Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics Wenjian Yu, Zeyi Wang, Xianlong Hong An Improved method for Fast Noise Estimation based on Net Segmentation Chih-Liang Huang, Aurobindo Dasgupta Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current H.-Y. Song, S. Bohidar, R. Iris Bahar, Joel Grodstein An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk Venkatesan Rajappan, Sachin S. Sapatnekar 2.1 Power Optimization A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe Precomputation-based Guarding for Dynamic and Leakage Power Reduction Afshin Abdollahi, Massoud Pedarm, Farzan Fallah, Indradeep Ghosh Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits Saravanan Rajapandian, Zheng Xu, K. L. Shepard Low Power Adder with Adaptive Supply Voltage Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File Nestoras Tzartzanis, William W. Walker 2.2 Invited Session: Gene Chip Design Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices Rastislav Levicky Design Flow Enhancements for DNA Arrays Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alex Z. Zelikovsky 2.3 System Level Design Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs Vikas Chandra, Gary Carpenter, Jeff Burns Interface Synthesis using Memory Mapping for an FPGA Platform Manev Luthra, Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau Efficient Synthesis of Networks On Chip Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli Reducing Compilation Time Overhead in Compiled Simulators Mehrdad Reshadi, Nikil Dutt 3.1 Systems Performance Profiling Interrupt Handler Performance through Kernel Instrumentation Branden Moore, Thomas Slabach, Lambert Schaelicke Design and Performance of Compressed Interconnects for High Performance Servers Krishna Kant, Ravi Iyer Routed Inter-ALU Networks for ILP Scalability and Performance Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger 3.2 Micro Processor Test & Diagnosis Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor Joel Grodstein, Dilip Bhavsar, Vijay Bettada, Richard Davies Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makr Multiple Fault Diagnosis Using n-Detection Tests Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski 3.3 Physical Design A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura Physical Design of the "2.5D" Stacked System Yangdong (Steven) Deng, Wojciech Maly Flow-Based Cell Moving Algorithm for Desired Cell Distribution Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh 4.1 Performance Optimization NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors Byeong Kil Lee, Lizy Kurian John Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan Pipelined Multiplicative Division with IEEE Rounding Guy Even, Peter-M. Seidel 4.2 Clock & Signal Distribution Design of Resonant Global Clock Distributions Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links Ganesh Balamurugan, Naresh Shanbhag A Mixed-Mode Delay-Locked-Loop Architecture Daniel Eckerbert, Lars "J." Svensson, Per Larsson-Edefors Optimal Inductance for On-chip RLC Interconnections Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester 4.3 Performance and Power-Driven Physical Design Spec Based Flip-Flop And Buffer Insertion Nataraj Akkiraju, Mosur Mohan A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization N. Ranganathan, Ashok K. Murugavel A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing Rishi Chaturvedi, Jiang Hu 5.1 Instruction Execution Hardware-based Pointer Data Prefetcher Shih-Chang Lai, Shih-Lien Lu A Dependence Driven Efficient Dispatch Scheme Sriram Nadathur, Akhilesh Tyagi An Efficient VLIW DSP Architecture for Baseband Processing Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen Dynamic Thread Resizing for Speculative Multithreaded Processors Mohamed Zahran, Manoj Franklin 5.2 Invited Session: Test Compression Technology Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities Bernd Koenemann XMAX: X-Tolerant Architecture for MAXimal Test Compression Subhasish Mitra, Kee Sup Kim Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs Janusz Rajski, Jerzy Tyszer 5.3 Physical Design for Regular Fabrics and FPGA's Non-Crossing OBDDs for Mapping to Regular Circuit Structures Aiqun Cao, Cheng-Kok Koh Interconnect Estimation for FPGAs under Timing Driven Domains Parivallal Kannan, Dinesh Bhatia ROAD : An Order-Impervious Optimal Detailed Router for FPGAs Hasan Arslan, Shantanu Dutt 6.1 Array Design Optimization Reducing dTLB Energy Through Dynamic Resizing V. Delaluz, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan Distributed Reorder Buffer Schemes for Low Power Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose Virtual Page Tag Reduction for Low-power TLBs Peter Petrov, Alex Orailoglu Dynamic Cluster Resizing José González, Antonio González 6.2 Test Compaction Independent Test Sequence Compaction through Integer Programming Petros Drineas, Yiorgos Makris On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty Static Test Compaction for Multiple Full-Scan Circuits Irith Pomeranz, Sudhakar M. Reddy A Method to Find Don’t Care Values in Test Sequences for Sequential Circuits Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz 6.3 Invited Session: Techniques for Synthesizing into Fabrics Simplifying SoC design with the Customizable Control Processor Platform C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo Bergamaschi, Bob Lynch, Santosh Gaur Structured ASICs: Opportunities and Challenges Behrooz Zahiri System LSI Implementation Fabrics for the Future (special panel discussion) Sinan Kaptanoglu 7.1 Hardware Partitioning Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan Dongku Kang, Mark C. Johnson, Kaushik Roy SCATOMi : Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture Young-Su Kwon, Bong-Il Park, Chong-Min Kyung A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units Kaushal R. Gandhi, Nihar R. Mahapatra 7.2 Energy-Aware Design and Application KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths Chandramouli Gopalakrishnan, Srinivas Katkoori A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits Madhubanti Mukherjee, Ranga Vemuri Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks Farhad Ghasemi-Tari, Peng Rong, Massoud Pedram 7.3 Invited Session: High-Speed Design Issues and Test Challenges CMOS High-Speed I/Os - Present and Future M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John Edmondson, John Poulton Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors K. Kiziloglu, S. Seetharaman, K.W. Glass, C. Bil, H.V. Duong, G. Asmanis Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems Mike Li, Jan Wilstrup 8.1 Efficiency and Reliability Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim Exploiting Microarchitectural Redundancy For Defect Tolerance Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger Reducing Multimedia Decode Power using Feedback Control Zhijian Lu, John Lach, Mircea Stan, Kevin Skadron 8.2 Novel Methods in Logic Synthesis Structural Detection of Symmetries in Boolean Functions Guoqiang Wang, Andreas Kuehlmann, Alberto Sangiovanni-Vincentelli Boolean Decomposition Based on Cyclic Chains Elena Dubrova, Maxim Teslenko, Johan Karlsson SAT-Based Algorithms for Logic Minimization Samir Sapra, Michael Theobald, Edmund Clarke 9.1 Communications and Context Management Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels Anand Selvarathinam, Euncheol Kim, Gwan Choi Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches Sudeep Pasricha, Alex Veidenbaum Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files Santithorn Bunchua, D. Scott Wills, Linda M. Wills xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini 9.2 Board Test and Power-Aware Test Aggressive Test Power Reduction Through Test Stimuli Transformation Ozgur Sinanoglu, Alex Orailoglu Power-Time Tradeoff in Test Scheduling for SoCs Mehrdad Nourani, James Chin Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity M. H. Tehranipour, N. Ahmed, M. Nourani TOP
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