ICCD PROCEEDINGS 2005, IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN



	Welcome Message Organizing Committee Program Committee Additional Reviewers Keynote Presentation Latency Lags Bandwidth Professor David Patterson - University of California at Berkeley 1.1 Power and Thermal Considerations in Processor Design (I) Temperature-Dependent Optimization of Cache Leakage Power Dissipation Peng Li, Yangdong Deng and Larry Pileggi - Texas A&M University Architectural Considerations for Energy Efficiency: Case Study of Viterbi Decoder ACS Unit Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija - University of California, Davis Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines Anahita Shayesteh, Eren Kursun, Tim Sherwood, Suleyman Sair, Glenn Reinman - University of California, Los Angeles Analytical Model for Sensor Placement on Microprocessors Kyeong-Jae Lee, Kevin Skadron - University of Virginia 1.2 Interconnect Prediction and Optimization Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement Qinghua Liu, Malgorzata Marek-Sadowska - University of California, Santa Barbara Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li and Soohong Kim - Cadence Design Systems X-Routing using Two Manhattan Route Instances Seraj Ahmad, Nikhil Jayakumar, VIjay Balasubramanian, Edward Hursey, Sunil P Khatri, Rabi Mahapatra - Texas A&M University 1.3 System-Level Architecture Hardware Support for Bulk Data Movement in Server Platforms Li Zhao, Laxmi Bhuyan - University of California, Riverside Ravi Iyer, Srihari Makineni, Don Newell - Communications Technology Lab, Intel Counter-Based Cache Replacement Algorithms Mazen Kharbutli and Yan Solihin - North Carolina State University Utilizing Horizontal and Vertical Parallelism Using a No-Instruction-Set Compiler and Custom Datapaths Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski - Center for Embedded Computer Systems (CECS) Panel Discussion Are Today's Verification Tools Able to Meet Current Design Challenges? Rich Faris - Real Intent Ken Larsen - Mentor Graphics Harry Foster - Jasper Stuart Swan - Cadence Tom Anderson - Synopsys 2.1 Power Aware System Design Energy-Efficient Color Approximation for Digital LCD Interfaces Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino - Politecnico di Torino Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini - Urbino University LCD DISPLAY ENERGY REDUCTION BY USER MONITORING Vasily Moshnyaga, Eiji Morikawa - Fukuoka University Frame Buffer Energy Optimization by Pixel Prediction Kimish Patel, Enrico Macii, Massimo Poncino - Politecnico di Torino Energy and Performance Analysis of Mapping Parallel Multi-threaded Tasks for An On-Chip Multi-Processor System Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede - University of California, Los Angeles Near-memory Caching for Improved Energy Consumption Nevine AbouGhazaleh, Bruce Childers, Daniel Mosse, Rami Melhem - University of Pittsburgh 2.2 Physical-Aware System-Level Analysis and Synthesis Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization Yuanfang Hu, Hongyu Chen, and Chung-Kuan Cheng - University of California, San Diego A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management Shrirang Yardi, Karthik Channakeshava, Micheal S Hsiao, Thomas Martin, Dong S. Ha - Virginia Tech Scalable System Design via Time Budgeting: Complexity Analysis and Dual Vt Technology Case Study Soheil Ghiasi, Po-Kuan Huang - University of California, Davis Efficient Thermal Simulation For Run-Time Temperature Tracking and Management Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon -X.D. Tan, and Jun Yang - University of California, Riverside 2.3 SOC Test Methods A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs Anuja Sehgal, Sule Ozev, and Krishnendu Chakrabarty - Duke University Concurrent Core Test for SOC Using Merged Test Set and Scan Tree Gang Zeng and Hideo Ito - Chiba University A Novel Test Compaction Technique for Responses with Unknown Values Mango C.-T. Chao, Seongmoon Wang, Srimat T. Chakradhar, and Kwang-Ting Cheng - NEC Labs., America Accurate Diagnosis for Multiple Defects Supporting Logic Reconfiguration Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng - University of California, Santa Barbara Quick Scan Chain Diagnosis Using Signal Profiling Jheng-Syun Yang and Shi-Yu Huang - National Tsing-Hua University, Taiwan Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits Fang Liu, Sule Ozev - Duke University 3.1 Reliable Circuit Design Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration Song Peng and Rajit Manohar - Cornell University Error-tolerance Memory Microarchitecture via Dynamic Multithreading Redundancy Lei Wang - University of Connecticut A Soft Error Monitor Using Switching Current Detection Patrick Ndai, Amit Agarwal, Qikai Chen and Kaushik Roy - Purdue University 3.2 High Level Synthesis Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr - RWTH-Aachen Statistical Analysis Driven Synthesis of Asynchronous Systems Koji Ohashi, Mineo Kaneko - Japan Advanced Institute of Science and Technology Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy - Purdue University 3.3 Verification of SOCs with Datapaths and Software Exploiting Vanishing Polynomials for Equivalence Verification of Fixed-Size Arithmetic Datapaths Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan - University of Utah Incorporating Efficient Assertion Checkers into Hardware Emulation and Simulation Marc Boulé and Zeljko Zilic - McGill University Assertion Checking of Behavioral Descriptions with Non-linear Solver Inigo Ugarte and Pablo Sanchez - University of Cantabria File System Interfaces for Embedded Software Development Bhanu Pisupati, Geoffrey Brown - Indiana University Keynote Presentation at the Computer History Museum (Mountain View) Yesterday and Tomorrow: A View on Progress in Computer Design Professor Michael J. Flynn - Stanford University 4.1 Low Power Circuit Architecture Ripple-Precharge TCAM: A Low-Power Solution for Network Search Engines Deepak S Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara - University of Texas at Dallas Low- and Ultra Low-Power Arithmetic Units: Design and Comparison Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija - University of California, Davis A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors Muhammad Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea Ismail, Vivek De - Intel Corporation A Low-Power Design of a 90-nm Processor Core: SH-X2 Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, and Toshihiro Hattori - Hitachi Ltd. 4.2 Emerging Design Styles And Applications Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton, Mark R. Greenstreet, Steven J.E. Wilton - University of British Columbia Algorithmic and Architectural Design Methodology for Particle Filters in Hardware Aswin Sankaranarayanan, Rama Chellappa and Ankur Srivastava - University of MD, Dept of ECE ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology Wei Zhang, Niraj K. Jha - Princeton University Automatic Synthesis of Composable Sequential Quantum Boolean Circuits Li-Kai Chang; Fu-Chiung Cheng - Tatung University 4.3 Formal Verification - From Hardware to Software (Invited) Model Checking C Programs Using F-Soft Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay Ganai, Vineet Kahlon, Chao Wang, Zijiang Yang - NEC Labs America Dealing with I/O Devices in the Context of Pervasive System Verification Mark Hillebrand Towards the Formal Verification of Lower System Layers in Automotive Systems Sven Beyer, Peter BÃ¶hm, Michael Gehrke, Mark Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang Paul 5.1 Cache Memory Architecture Restrictive Compression Techniques to Increase Level 1 Cache Capacity Prateek Pujara, Aneesh Aggarwal - Binghamton University The TM3270 Media-Processor Data Cache Jan-Willem van de Waerdt, Jean-Paul van Itegem, Hans van Antwerpen - Philips Semiconductors, San Jose, CA, USA and Stamatis Vassiliadis - TU Delft, Computer Engineering, Delft, The Netherlands Mitigating Soft Error in Highly Associative Cache with CAM-based Tag Luong D. Hung, Masahiro Goshima, Shuichi Sakai - The University of Tokyo 5.2 Gate Timing and Power Analysis VGTA: Variation_Aware Gate Timing Analysis Soroush Abbaspour, Hanif Fatemi, Massoud Pedram - University of Southern California Exact Lower Bound for the Number of Switches in Series to Implement a Combinational Logic Cell F.R.Schneider, R.P.Ribas, S.S.Sapatnekar and A.I.Reis - UFRGS Brazil Waveform Independent Gate Models for Accurate Timing Analysis Peng Li - Texas A&M University Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis Fei Hu and Vishwani D. Agrawal - Auburn University 5.3 Performance Modeling Methods for Modeling Resource Contention on Simultaneous Multithreading Processors Tipp Moseley, Joshua L. Kihm, Daniel A. Connors, Dirk Grunwald - University of Colorado Using Scratchpad to exploit object locality in Java Carl S. Lebsack and J. Morris Chang - Iowa State University Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture Khaled Z. Ibrahim - Suez Canal University Simulating Java Commercial Throughput Workload: A Case Study Yue Luo, Lizy K. John - University of Texas at Austin 6.1 Low Voltage Design Minimum Energy Near-threshold Network of PLA based Design Nikhil Jayakumar Sunil P Khatri - Texas A&M University Robust Design of High Fan-in/out Subthreshold Circuits Jinhui Chen, Lawrence T. Clark, Yu(Kevin) Cao - Arizona State University A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee - University of California, Santa Barbara A Feasibility Study of Subthrehold SRAM Across Technology Generations Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy - Purdue University 6.2 Physical-Aware Circuit Design Variability-Driven Buffer Insertion Considering Correlations Azadeh Davoodi, Ankur Srivastava - University of Maryland A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits Valmiki Mukherjee, Saraju P. Mohanty and Elias Kougianos - University of North Texas Supply Voltage Degradation Aware Placement Andrew B. Kahng, Bao Liu and Qinke Wang - University of California, San Diego Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners Anuradha Agarwal and Ranga Vemuri - University of Cincinnati 6.3 Verification and Test for Sequential Circuits and Delay Fault Models Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults Manan Syal, Rajat Arora, Michael S. Hsiao - Virginia Tech Case Study of ATPG-Based Bounded Model Checking: Verifying USB 2.0 IP Core Qiang Qiang, Chia-Lun Chang, Daniel G. Saab and Jacob A. Abraham Case - Western Reserve University Towards finding path delay fault tests with high test efficiency using ZBDDs M. K. Michael, K. Christou and S. Tragoudas - University of Cyprus Quality Transition Fault Tests Suitable for Small Delay Defects M.M. Vaseekar Kumar, S.Tragoudas - Southern Illinois University, Carbondale A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals N. Devtaprasanna, A. Gunda, P. Krishnamurthy and S. M. Reddy - University of Iowa A Flexible Logic BIST Scheme for Multiple-Clock Circuits Laung-Terng (L.-T.) Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo Kyushu, I. Pomeranz - Institute of Technology Hardware Efficient LBIST With Complementary Weights Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng - University of Illinois at Urbana-Champaign 7.1 New Memory Technologies (Invited) FRAM Rick Bailey, Ramtron International Corporation Thermal MRAM Dr. James G. Deak, NVE Corporation Future Directions of Non-Volatile Memory technologies Mr. Albert Fazio, Intel Corporation 7.2 Panel Discussion: Chip Multiprocessing Moderator: Greg Byrd - North Carolina State University Pradeep Dubey - Intel Jan Gray - Microsoft Rick Hetherington - Sun Charlie Johnson - IBM Chuck Moore - AMD Kunle Olukutun - Stanford University 8.1 High Performance Designs A High Performance Reconfigurable and Sub-Pipelined Architecture for AES Hua Li and Jianzhou Li - University of Lethbridge Distortionless Electrical Signaling for Speed-of-Light On-Chip Communications Hongyu Chen and Chung-Kuan Cheng - University of California, San Diego Partial-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto - Waseda University Fast Minimum and Maximum Selection Anatoly I. Grushin - Intel Corporation 8.2 Future VLSI Technologies and Their Impact Three-Dimensional Cache Design Exploration Using 3DCacti Yuh-Fang Tsai, Yuan Xie, Vijaykrishnan N.,and Mary J. Irwin - Penn State University Implementing Caches in a 3D Technology for High Performance Processors Kiran Puttaswamy, Georgia Tech Gabriel H. Loh, - Georgia Institute of Technology Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors Wenjing Rao, Alex Orailoglu, Ramesh Karri - University of California, San Diego 8.3 Architecture for Verifiability (Invited) Formal Verification and its Impact on the Snooping versus Directory Protocol Debate Milo M. K. Martin - Department of Computer and Information Science, University of Pennsylvania Deployment of Better Than Worst-Case Design: Solutions and Needs Todd Austin, Valeria Bertacco - University of Michigan, Ann Arbor 9.1 Low Power Circuit Architecture (II) Benefits and Costs of Power-Gating Technique Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif - University of California, Santa Barbara A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS Maryam Ashouei, Abhijit Chatterjee, Adit. D. Singh, and Vivek De - Georgia Inst. of Technology A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction J.B. Kuang, H.C. Ngo, K.J. Nowka, J.C. Law, R.V. Joshi - IBM 9.2 RF Wireless Technologies (Invited) Tutorial on RF Technologies Dominik Schmidt, Intel Corporation 9.3 Formal Verification Methods State Set Management for SAT-based Unbounded Model Checking Kameshwar Chandrasekar and Michael S. Hsiao - Virginia Tech Reconsidering CEGAR: Learning Good Abstractions without Refinement Anubhav Gupta, Edmund Clarke - Carnegie Mellon University Formal Verification of Parametric Multiplicative Division Implementations Nikhil Kikkeri and Peter-Michael Seidel - Southern Methodist University Challenges in the Formal Verification of Complete State-of-the-Art Processors Nathaniel Ayewah, Sven Beyer, Nikhil Kikkeri and Peter-Michael Seidel - Southern Methodist University 10.1 Power and Thermal Considerations in Processor Design (II) ReCast: Boosting Tag Line Buffer Coverage in Low Power High-Level Caches for Free Won-Ho Park, Andreas Moshovos, Babak Falsafi - University of Toronto Load-Store Queue Management: an Energy Efficient Design based on a State Filtering Mechanism F. Castro, D. Chaver, L. Pinuel, M. Prieto, M. C. Huang, F. Tirado - Complutense University of Madrid Optimizing the Thermal Behavior of Subarrayed Data Caches Johnsy K. John, Jie S. Hu, and Sotirios G. Ziavras - New Jersey Institute of Technology VALVE: Variable Length Value Encoding for Off-Chip Data Buses Dinesh C Suresh, Banit Agrawal, Walid A Najjar, Jun Yang - University of California, Riverside Monitoring Temperature in FPGA based SoCs Siva Velusamy, John Lach, Kevin Skadron - University of Virginia 10.2 Instruction Issue, Scheduling and Prediction Reducing the Energy of Speculative Instruction Schedulers Yongxiang Liu, Gokhan Memik, and Glenn Reinman - University of California, Los Angeles A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation Marco A. Ramírez, Adrian Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero - UPC-DAC Power-Efficient Wakeup Tag Broadcast Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin - State University of New York at Binghamton Symbiotic Subordinate Threading Rania Mameesh, Manoj Franklin - University of Maryland Memory Bank Predictors Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio Gonzalez - UPC 11.1 Circuit Consideration in Processor Design H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication Xizhen Xu, Sotirios Ziavras - New Jersey Institute of Technology Temperature-Sensitive Loop Parallelization for Chip Multiprocessors Sri Hari Krishna Narayanan, Guilin Chen, Mahmut Kandemir - Penn State University Broadband Impedance Matching for Inductive Interconnect in VLSI Packages Brock J. LaMeres, Sunil P. Khatri -Texas A&M University Temperature-Aware Voltage Islands Architecting in System-on-Chip Design W.-L. Hung, G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada and J. Conner - Microsystems Design Laboratory 11.2 Logic Optimization Temporal Decomposition for Logic Optimization Nathan Kitchen and Andreas Kuehlmann - University of California, Berkeley Attacking Control Overhead to Improve Synthesized Asynchronous Circuit Performance Luis A. Plana, Sam Taylor and Doug Edwards - University of Manchester An Improved Approach for Alternative Wires Identification Yung-Chih Chen and Chun-Yao Wang - Tsing Hua University TOP
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