Sunday, October 2, 2005

New Developments in Embedded System Design

Abstract

Embedded System Design is rapidly moving versus Electronic System Level (ESL) approaches that promise to deliver a complete SOC/embedded system design from system requirements down to silicon and software implementation.

We focus on both design and verification aspects of ESL methodologies in order to clarify the current reality from an embedded system designer perspective. In the design track we cover ESL design fundamentals, trends in SOC architectures, on-chip communication, design space exploration, synthesis of hardware and software, integration challenges.

With respect to verification, we first discuss recent developments in applying Bounded Model Checking techniques to software. Finally, we discuss modeling of embedded systems as hybrid (mixed discrete-continuous) systems, and techniques to analyze such hybrid systems formally.

Keynote Speakers

Communication Oriented Design Flow
Marcello Coppola - ST Microelectronics, Grenoble, France

• On-Chip Communication Architectures: From Spaghetti to Bus and From Bus to NoC
• STBUS: A Solution for SOC today, Spidergon: A Research for NOC today
• On-Chip Communication Protocols
• On-Chip Communication QoS
• On-Chip Communication Design Flow: Today and Tomorrow

Biography
Marcello Coppola is the head of the Grenoble research lab within the Advanced System Technology department at STMicroelectronics-Grenoble. His research interests include discrete event simulation, networks on chip and modeling of multiprocessor systems on chip. Coppola received a Laurea degree in computer science from the University of Pisa, Italy.

System on Chip Architectures and Design Space Exploration
Marcello Lajolo - NEC Laboratories America, Princeton, NJ, USA

• New Trends in SOC Organization
• Design Space Exploration
• Hardware/Software Partitioning and Integration Challenges

Biography
Marcello Lajolo received the Dr. Eng. and the Ph.D. degrees in Electrical Engineering from the Politecnico di Torino, Italy, in 1995 and 1999, respectively. He is currently a Senior Research Staff Member at NEC Laboratories America, Inc. in Princeton, NJ where he leads the effort on single/multiprocessor interface synthesis starting from system level specifications. His research interests concern the development of methodologies and tools for electronic system level design. He focuses in particular on design and synthesis of reusable platforms, networks on chip and hardware/software integration challenges.

Software for Embedded Systems
Tony Givargis - University of California, Irvine, CA, USA

• Code Serialization (The Phantom C Compiler)
• Software Synthesis Techniques (Monolithic RTOS/Application Code)
• Software Peripherals (Entire Platforms in Software)
• Platform-Aware Code Transformations

Biography
Dr. Tony Givargis received his B.S. and Ph.D. in Computer Science from the University of California, Riverside in 1997 and 2001 respectively. He is currently an Assistant Professor in the Department of Computer Science, and a member of the Center for Embedded Computer Systems, at the University of California, Irvine. Dr. Givargis and his team at Irvine, are researching issues related to Realtime Operating System (RTOS) synthesis, high-confidence embedded software, serializing compilers, and code transformations techniques for efficient software to hardware migration. Dr. Givargis is a coauthor of a textbook entitled "Embedded System Design: A Unified Hardware/Software Introduction" and has published extensively in the general areas of embedded system research.

Software and Hybrid System Verification
Franjo Ivancic - NEC Laboratories America, Princeton, NJ, USA

• Bounded Model Checking for Software
• Predicate Abstraction
• Modeling and Analysis of Hybrid Systems

Biography
Franjo Ivancic is currently a Research Staff Member at NEC Laboratories America in Princeton, NJ. Prior to joining NEC, he received his Ph.D. and MSE degrees in Computer and Information Science from the University of Pennsylvania in Philadelphia, PA. Earlier, he received his diploma (Dipl.-Inform.) degree from the Rheinische Friedrich-Wilhelms-University in Bonn, Germany, for his research performed at the Fraunhofer Institute in St. Augustin, Germany. His areas of research include software verification, model checking, formal modeling and analysis of hybrid systems, and design automation for embedded software. He received the Morris and Dorothy Rubinoff dissertation award from the University of Pennsylvania.

Monday, October 3, 2005

Keynote Presentation

Latency Lags Bandwidth
Professor David Patterson - University of California at Berkeley

Abstract
As I review performance trends, I am struck by a consistent theme across many technologies over many years: bandwidth improves much more quickly than latency for four different technologies: disks, networks, memories and processors. A rule of thumb to quantify the imbalance is: Bandwidth improves by more than the square of the improvement in latency.
This talk lists a half-dozen performance milestones to document this observation, many reasons why it happens, a few ways to cope with it, and two small examples of how you might design systems differently if you kept this simple rule of thumb in mind.

Biography
David Patterson has been Professor of Computer Science at U.C. Berkeley since 1977. He is one of the pioneers of both Reduced Instruction Set Computers (RISC) and Redundant Arrays of Inexpensive Disks (RAID), which are widely used. He co-authored five books, including two with John Hennessy, that have been popular in graduate and undergraduate courses since 1990. Past chair of the Computer Science Department at U.C. Berkeley and the Computing Research Association, he is currently President of the Association for Computing Machinery and serves on the Information Technology Advisory Committee for the U.S. President. His work was recognized by education and research awards from ACM and IEEE and by election to the National Academy of Engineering. In the past year he shared Japan's Computer & Communication award with Hennessy and was named to the Silicon Valley Engineering Hall of Fame.

1.1 Power and Thermal Considerations in Processor Design (I) 

• Temperature-Dependent Optimization of Cache Leakage Power Dissipation
  Peng Li, Yangdong Deng and Larry Pileggi - Texas A&M University
• Architectural Considerations for Energy Efficiency: Case Study of Viterbi Decoder ACS Unit
  Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija - University of California, Davis
• Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
  Anahita Shayesteh, Eren Kursun, Tim Sherwood, Suleyman Sair, Glenn Reinman - University of California, Los Angeles
• Analytical Model for Sensor Placement on Microprocessors
  Kyeong-Jae Lee, Kevin Skadron - University of Virginia

1.2 Interconnect Prediction and Optimization

• Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
  Qinghua Liu, Malgorzata Marek-Sadowska - University of California, Santa Barbara
• Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
  Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li and Soohong Kim - Cadence Design Systems
• X-Routing using Two Manhattan Route Instances
  Seraj Ahmad, Nikhil Jayakumar, VIjay Balasubramanian, Edward Hursey, Sunil P Khatri, Rabi Mahapatra - Texas A&M University

1.3 System-Level Architecture 

• Hardware Support for Bulk Data Movement in Server Platforms
  Li Zhao, Laxmi Bhuyan - University of California, Riverside
  Ravi Iyer, Srihari Makineni, Don Newell - Communications Technology Lab, Intel 
• Counter-Based Cache Replacement Algorithms
  Mazen Kharbutli and Yan Solihin - North Carolina State University
• Utilizing Horizontal and Vertical Parallelism Using a No-Instruction-Set Compiler and Custom Datapaths
  Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski - Center for Embedded Computer Systems (CECS)

Lunch
Panel Discussion: Are Today's Verification Tools Able to Meet Current Design Challenges?

Abstract
With the ever increasing growth of size and complexity of digital designs, tools have just kept pace. Design engineers bare the brunt of the problem. To make use of dynamic verification, designers invest as much or more time into their test benches as they do the design they are creating. For static or formal verification, large designs with complex state spaces have challenged even the most powerful formal tools. What changes are coming in the design and EDA spaces that will improve this situation? What is the right mix of dynamic and static verification for the future? Formal Verification in Industry - What Works, What Doesn't and Where is it Headed?

Moderator: Richard Goering - EETimes
Rich Faris - Real Intent
Ken Larsen - Mentor Graphics
Harry Foster - Jasper
Stuart Swan - Cadence
Tom Anderson - Synopsys

2.1 Power Aware System Design

• Energy-Efficient Color Approximation for Digital LCD Interfaces
  Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino - Politecnico di Torino
• Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms
  Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini - Urbino University
• LCD DISPLAY ENERGY REDUCTION BY USER MONITORING
  Vasily Moshnyaga, Eiji Morikawa  - Fukuoka University
• Frame Buffer Energy Optimization by Pixel Prediction
  Kimish Patel, Enrico Macii, Massimo Poncino - Politecnico di Torino
• Energy and Performance Analysis of Mapping Parallel Multi-threaded Tasks for An On-Chip Multi-Processor System
  Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede - University of California, Los Angeles
• Near-memory Caching for Improved Energy Consumption
  Nevine AbouGhazaleh, Bruce Childers, Daniel Mosse, Rami Melhem - University of Pittsburgh

2.2 Physical-Aware System-Level Analysis and Synthesis

• Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization
  Yuanfang Hu, Hongyu Chen, and Chung-Kuan Cheng - University of California, San Diego
• A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
  Shrirang Yardi, Karthik Channakeshava, Micheal S Hsiao, Thomas Martin, Dong S. Ha - Virginia Tech
• Scalable System Design via Time Budgeting: Complexity Analysis and Dual Vt Technology Case Study
  Soheil Ghiasi, Po-Kuan Huang - University of California, Davis
• Efficient Thermal Simulation For Run-Time Temperature Tracking and Management
  Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon -X.D. Tan, and Jun Yang - University of California, Riverside

2.3 SOC Test Methods

• A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
  Anuja Sehgal, Sule Ozev, and Krishnendu Chakrabarty - Duke University
• Concurrent Core Test for SOC Using Merged Test Set and Scan Tree
  Gang Zeng and Hideo Ito - Chiba University
• A Novel Test Compaction Technique for Responses with Unknown Values Mango
  C.-T. Chao, Seongmoon Wang, Srimat T. Chakradhar, and Kwang-Ting Cheng - NEC Labs., America
• Accurate Diagnosis for Multiple Defects Supporting Logic Reconfiguration
  Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng - University of California, Santa Barbara
• Quick Scan Chain Diagnosis Using Signal Profiling
  Jheng-Syun Yang and Shi-Yu Huang - National Tsing-Hua University, Taiwan
• Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits
  Fang Liu, Sule Ozev - Duke University

3.1 Reliable Circuit Design

• Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
  Song Peng and Rajit Manohar - Cornell University
• Error-tolerance Memory Microarchitecture via Dynamic Multithreading Redundancy
  Lei Wang - University of Connecticut
• A Soft Error Monitor Using Switching Current Detection
  Patrick Ndai, Amit Agarwal, Qikai Chen and Kaushik Roy - Purdue University

3.2 High Level Synthesis

• Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
  Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr - RWTH-Aachen
• Statistical Analysis Driven Synthesis of Asynchronous Systems
  Koji Ohashi, Mineo Kaneko - Japan Advanced Institute of Science and Technology
• Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
  Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi, and Kaushik Roy - Purdue University

3.3 Verification of SOCs with Datapaths and Software

• Exploiting Vanishing Polynomials for Equivalence Verification of Fixed-Size Arithmetic Datapaths
  Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan - University of Utah
• Incorporating Efficient Assertion Checkers into Hardware Emulation and Simulation
  Marc Boulé and Zeljko Zilic - McGill University
• Assertion Checking of Behavioral Descriptions with Non-linear Solver
  Inigo Ugarte and Pablo Sanchez - University of Cantabria
• File System Interfaces for Embedded Software Development
  Bhanu Pisupati, Geoffrey Brown - Indiana University

Reception and Keynote Presentation at the Computer History Museum (Mountain View)

Yesterday and Tomorrow: A View on Progress in Computer Design
Professor Michael J. Flynn - Stanford University

Abstract
Some 50 years ago saw a series of rapid advances in design automation technology setting the stage for generations of reliable computers. Over the intervening years progress in the field continued to deal with the advancing complexity of the technology. This success in design automation was based on capturing or encapsulating complex designs into components to be managed in a larger design. On the other hand, in the past, power was never seen as a limitation yet this now looms as a major problem.
Looking at the future, designer productivity and design complexity remain a central limitation on product development especially for specialized system applications (SOC type). Power presents a new challenge especially to the same emerging system applications. We look at these issues both in the context of the past and possibilities for the future.

Biography
Michael J Flynn received his BS from Manhattan College, MS from Syracuse University and PhD from Purdue University. He began his engineering career in 1955 at IBM as a designer of mainframe computers such as the 7090 and System 360 Model 91. He became Professor of Electrical Engineering at Stanford in 1975 where he set up the Stanford Architecture and Arithmetic group. He has authored or co-authored 5 books and over 250 professional papers.
Prof. Flynn founded both of the specialist organization on Computer Architecture: the IEEE Computer Society's Technical Committee on Computer Architecture and the ACM's SIGARCH. He is a fellow of IEEE and ACM and winner of the ACM/IEEE Eckert--Mauchly Award and the IEEE Computer Society's Harry Goode Award.

Tuesday, October 4, 2005

4.1 Low Power Circuit Architecture

• Ripple-Precharge TCAM: A Low-Power Solution for Network Search Engines
  Deepak S Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara - University of Texas at Dallas
• Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
  Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija - University of California, Davis
• A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
  Muhammad Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea Ismail, Vivek De - Intel Corporation
• A Low-Power Design of a 90-nm Processor Core: SH-X2
  Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, and Toshihiro Hattori - Hitachi Ltd.

4.2 Emerging Design Styles And Applications

• Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
  Bradley R. Quinton, Mark R. Greenstreet, Steven J.E. Wilton - University of British Columbia
• Algorithmic and Architectural Design Methodology for Particle Filters in Hardware
  Aswin Sankaranarayanan, Rama Chellappa and Ankur Srivastava - University of MD, Dept of ECE
• ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
  Wei Zhang, Niraj K. Jha - Princeton University
• Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
  Li-Kai Chang; Fu-Chiung Cheng - Tatung University

4.3 Formal Verification - From Hardware to Software (Invited)

• Model Checking C Programs Using F-Soft
  Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay Ganai, Vineet Kahlon, Chao Wang, Zijiang Yang - NEC Labs America
• Dealing with I/O Devices in the Context of Pervasive System Verification
  Mark Hillebrand
• Towards the Formal Verification of Lower System Layers in Automotive Systems
  Sven Beyer, Peter Böhm, Michael Gehrke, Mark Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang Paul

5.1 Cache Memory Architecture

• Restrictive Compression Techniques to Increase Level 1 Cache Capacity
  Prateek Pujara, Aneesh Aggarwal - Binghamton University
• The TM3270 Media-Processor Data Cache
  Jan-Willem van de Waerdt, Jean-Paul van Itegem, Hans van Antwerpen - Philips Semiconductors, San Jose, CA, USA and Stamatis Vassiliadis - TU Delft, Computer Engineering, Delft, The Netherlands
• Mitigating Soft Error in Highly Associative Cache with CAM-based Tag
  Luong D. Hung, Masahiro Goshima, Shuichi Sakai - The University of Tokyo

5.2 Gate Timing and Power Analysis

• VGTA: Variation_Aware Gate Timing Analysis
  Soroush Abbaspour, Hanif Fatemi, Massoud Pedram - University of Southern California
• Exact Lower Bound for the Number of Switches in Series to Implement a Combinational Logic Cell
  F.R.Schneider, R.P.Ribas, S.S.Sapatnekar and A.I.Reis - UFRGS Brazil
• Waveform Independent Gate Models for Accurate Timing Analysis
  Peng Li - Texas A&M University
• Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
  Fei Hu and Vishwani D. Agrawal - Auburn University

5.3 Performance Modeling

• Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
  Tipp Moseley, Joshua L. Kihm, Daniel A. Connors, Dirk Grunwald - University of Colorado
• Using scratchpad to exploit object locality in Java
  Carl S. Lebsack and J. Morris Chang - Iowa State University
• Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture
  Khaled Z. Ibrahim - Suez Canal University
• Simulating Java Commercial Throughput Workload: A Case Study
  Yue Luo, Lizy K. John - University of Texas at Austin

6.1 Low Voltage Design

• Minimum Energy Near-threshold Network of PLA based Design
  Nikhil Jayakumar Sunil P Khatri - Texas A&M University
• Robust Design of High Fan-in/out Subthreshold Circuits
  Jinhui Chen, Lawrence T. Clark, Yu(Kevin) Cao - Arizona State University
• A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
  Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee - University of California, Santa Barbara
• A Feasibility Study of Subthrehold SRAM Across Technology Generations
  Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy - Purdue University

6.2 Physical-Aware Circuit Design

• Variability-Driven Buffer Insertion Considering Correlations
  Azadeh Davoodi, Ankur Srivastava - University of Maryland
• A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
  Valmiki Mukherjee, Saraju P. Mohanty and Elias Kougianos - University of North Texas
• Supply Voltage Degradation Aware Placement
  Andrew B. Kahng, Bao Liu and Qinke Wang - University of California, San Diego
• Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
  Anuradha Agarwal and Ranga Vemuri - University of Cincinnati

6.3 Verification and Test for Sequential Circuits and Delay Fault Models

• Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults
  Manan Syal, Rajat Arora, Michael S. Hsiao - Virginia Tech
• Case Study of ATPG-Based Bounded Model Checking: Verifying USB 2.0 IP Core
  Qiang Qiang, Chia-Lun Chang, Daniel G. Saab and Jacob A. Abraham Case - Western Reserve University
• Towards finding path delay fault tests with high test efficiency using ZBDDs
  M. K. Michael, K. Christou and S. Tragoudas - University of Cyprus
• Quality Transition Fault Tests Suitable for Small Delay Defects
  M.M. Vaseekar Kumar, S.Tragoudas - Southern Illinois University, Carbondale
• A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
  N. Devtaprasanna, A. Gunda, P. Krishnamurthy and S. M. Reddy - University of Iowa
• A Flexible Logic BIST Scheme for Multiple-Clock Circuits
  Laung-Terng (L.-T.) Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo Kyushu, I. Pomeranz - Institute of Technology
• Hardware Efficient LBIST With Complementary Weights
  Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng - University of Illinois at Urbana-Champaign

7.1 New Memory Technologies (Invited)

• FRAM
  Rick Bailey, Ramtron International Corporation
• Thermal MRAM
  Dr. James G. Deak, NVE Corporation
• Future Directions of Non-Volatile Memory technologies
  Mr. Albert Fazio, Intel Corporation

Banquet (Doubletree Hotel)

Panel Discussion: Chip Multiprocessing

Moderator: Greg Byrd - North Carolina State University
Pradeep Dubey - Intel
Jan Gray - Microsoft
Rick Hetherington - Sun
Charlie Johnson - IBM
Chuck Moore - AMD
Kunle Olukutun - Stanford University