Sunday, October 2, 2005
 Workshop on New Developments in Embedded System Design
01.00

Communication Oriented Design Flow
 Marcello Coppola
- ST Microelectronics, Grenoble, France

  System on Chip Architectures and Design Space Exploration
Marcello Lajolo -
NEC Laboratories America, Princeton, NJ, USA
03.00

Break

03.15 Software for Embedded Systems
Tony Givargis -
University of California, Irvine, CA, USA
  Software and Hybrid System Verification
Franjo Ivancic -
NEC Laboratories America, Princeton, NJ, USA
05.00 Session Ends
 

 Monday, October 3, 2005

09.00

Welcome and Opening Address

09.30 Keynote - David Patterson, University of California, Berkeley
10.30

Session 1.1
Power and Thermal Considerations in Processor Design

Session 1.2
Interconnect Prediction and Optimization
Session 1.3
System-Level Architecture
12.00

Lunch
Panel Discussion:  "Are Today's Verification Tools Able to Meet Current Design Challenges?"
 

01.30

 Session 2.1
Power Aware System Design

  Session 2.2
 
Physical-Aware System-Level Analysis and Synthesis
 Session 2.3
SOC Test Methods
03.30

Break

04.00  Session 3.1
Reliable Circuit Design

Session 3.2
High Level Synthesis

 Session 3.3
Verification of SOCs with Datapaths and Software
05.30 Break
06.00 Reception at the Computer History Museum (Mountain View)
Keynote - Michael Flynn, Stanford University
09.00 Session Ends
 

 Tuesday, October 4, 2005

08.00

Session 4.1
Low Power Circuit Architecture

Session 4.2
Emerging Design Styles And Applications
Session 4.3
Formal Verification - From Hardware to Software (Invited)
10.00

Break

10.30 Session 5.1
Cache Memory Architecture
Session 5.2
Gate Timing and Power Analysis
Session 5.3
Performance Modeling
12.00

Lunch
Speaker from Cadence

01.30 Session 6.1
Low Voltage Design


 
Session 6.2
Physical-Aware Circuit Design

 
Session 6.3
Verification and Test for Sequential Circuits and
Delay Fault Models
03.30

Break

04.00 Session 7
New Memory Technologies (Invited)
05.30

Break

06.00   Banquet (Doubletree Hotel)
Panel Discussion: Chip Multiprocessing
09.00

Session Ends

 

 Wednesday, October 5, 2005

08.00

Session 8.1
High Performance Designs

 

Session 8.2
Future VLSI Technologies and Their Impact
Session 8.3
Architecting for Verifiability (Invited)
10.00

Break

10.30 Session 9.1
Low Power
Circuit Architecture (II)
Session 9.2
RF Wireless Technologies (Invited)
Session 9.3
Formal verification Methods
12.30

Lunch

01.30 Session 10.1
Power and Thermal Considerations in Processor Design (II)
Session 10.2
Instruction Issue, Scheduling and Prediction
 
03.30

Break

04.00 Session 11.1
Circuit Consideration in Processor Design
Session 10.2
Instruction Issue, Scheduling and Prediction

 
 
06.00

Session Ends

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