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Sunday, October 2, 2005 |
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Workshop on New Developments in
Embedded System Design |
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01.00 |
Communication Oriented Design Flow
Marcello Coppola
- ST Microelectronics, Grenoble, France |
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System on Chip Architectures and
Design Space Exploration
Marcello Lajolo -
NEC Laboratories America, Princeton, NJ, USA |
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03.00 |
Break |
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03.15 |
Software for Embedded Systems
Tony Givargis - University of
California, Irvine, CA, USA |
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Software and Hybrid System
Verification
Franjo Ivancic -
NEC Laboratories America, Princeton, NJ, USA |
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05.00 |
Session Ends |
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Monday, October 3,
2005 |
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09.00 |
Welcome and Opening
Address |
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09.30 |
Keynote - David Patterson,
University of California, Berkeley |
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10.30 |
Session 1.1
Power and Thermal
Considerations in Processor Design
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Session 1.2
Interconnect Prediction and Optimization |
Session 1.3
System-Level
Architecture |
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12.00 |
Lunch
Panel Discussion: "Are
Today's Verification Tools Able to Meet Current Design Challenges?"
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01.30 |
Session
2.1
Power Aware System Design
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Session
2.2
Physical-Aware
System-Level Analysis and Synthesis |
Session
2.3
SOC Test Methods |
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03.30 |
Break |
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04.00 |
Session
3.1
Reliable Circuit Design |
Session 3.2
High Level Synthesis
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Session
3.3
Verification of SOCs with Datapaths and Software |
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05.30 |
Break |
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06.00 |
Reception at the Computer
History Museum (Mountain View)
Keynote - Michael Flynn, Stanford University |
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09.00 |
Session Ends |
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Tuesday,
October 4, 2005 |
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08.00 |
Session 4.1
Low Power Circuit Architecture |
Session 4.2
Emerging Design Styles And
Applications |
Session 4.3
Formal Verification - From
Hardware to Software (Invited) |
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10.00 |
Break |
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10.30 |
Session 5.1
Cache Memory Architecture |
Session 5.2
Gate Timing and Power Analysis |
Session 5.3
Performance Modeling |
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12.00 |
Lunch
Speaker from Cadence |
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01.30 |
Session 6.1
Low Voltage Design
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Session 6.2
Physical-Aware Circuit Design
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Session 6.3
Verification and Test for
Sequential Circuits and
Delay Fault Models |
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03.30 |
Break |
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04.00 |
Session 7
New Memory Technologies (Invited) |
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05.30 |
Break |
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06.00 |
Banquet (Doubletree Hotel)
Panel Discussion: Chip Multiprocessing |
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09.00 |
Session Ends |
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Wednesday,
October 5, 2005 |
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08.00 |
Session 8.1
High Performance Designs
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Session 8.2
Future VLSI Technologies and
Their Impact |
Session 8.3
Architecting for Verifiability
(Invited) |
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10.00 |
Break |
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10.30 |
Session 9.1
Low Power
Circuit Architecture (II) |
Session 9.2
RF Wireless Technologies (Invited) |
Session 9.3
Formal verification Methods |
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12.30 |
Lunch |
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01.30 |
Session 10.1
Power and Thermal Considerations
in Processor Design (II) |
Session 10.2
Instruction Issue, Scheduling and Prediction |
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03.30 |
Break |
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04.00 |
Session 11.1
Circuit Consideration in Processor
Design |
Session 10.2
Instruction Issue, Scheduling and Prediction
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06.00 |
Session Ends |
TOP
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