Dr.Reiner Hartenstein is CS professor at TU Kaiserslautern and consultant and authorized expert and referee on Information Technology. He was associate professor at Karlsruhe Institute of Technology where he had received all academic degrees, and was visiting professor at UC Berkeley. Reiner Hartenstein is IEEE life fellow, SDPS fellow, FPL fellow and recipient of several other awards. He is consultant and authorized expert and referee on Information Technology. In research he is credited to be the father of Reconfigurable Computing. He is author of the hardware language KARL, trailblazer for VHDL and Verilog. He is founder of three, and co-founder of two more successful international conference series, as well as founder of the Multi University VLSI Design Project „E.I.S.“, the German contribution to the Mead-&-Conway VLSI design revolution. He has published 14 books and more than 400 technical papers and has given numerous talks, including more than 200 invited talks and more than 20 keynote addresses.
Dr. Henkel received his Master and Ph.D ("Summa cum laude") degrees both from the Technical University of Braunschweig, Germany. He then joined the Computer & Communication Research Laboratories CCRL (now NEC Laboratories America) in Princeton, NJ, where he led various projects in the areas of low power system level design and advanced embedded architectures. In between, he had an appointment as a visiting professor at the University of Notre Dame, IN. Dr. Henkel is currently with Karlsruhe University (TH), Germany, where he is directing the Chair for Embedded Systems CES. He has served or is serving as a program committee member for major conferences in electronic design automation and embedded system design. In 2001 he served as a Program Chair for the IEEE/ACM Codes Hardware/Software Co-design Symposium and was a General of the same convention in 2002. Furthermore, he was a Program Chair for the 2002 IEEE Workshop on Rapid System Prototyping. In 2006 he served as a Program Chair for the IEEE/ACM Symposium on Low Power Electronics and Design (ISLPED) and in 2008 he served as the Program Chair for the IEEE Signal Processing Workshop. He has guest-edited special issues on hardware/software co-design in the IEEE Computer Magazine and on rapid system prototyping with Kluwer. He is currently an Associate Editor of the IEEE Transactions on VLSI Systems and the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems. He is a also steering committee member of ICCAD and he Chair of the IEEE Computer Society, Germany Section. In 2007 his edited book “Designing Embedded Processors – A Low Power Perspective” was published by Springer. Dr. Henkel holds nine US patents.
Edward Grochowski received his bachelor's degree in electrical engineering in 1985 and a master's degree in electrical engineering 1986, both from University of California at Berkeley. He joined Intel in 1986. He was a member of the design teams for four microprocessors: the 486, Pentium, Pentium II, and Itanium. He worked on microarchitectural techniques for energy-efficient chip multiprocessors in Intel's Microprocessor Research Labs and now he is currently working on a design of a future graphics processor.
Dr. Tom Conte received his Ph.D. from the University of Illinois at Urbana Champaign in 1992. His research is in the areas of manycore/multicore architectures, microprocessor architectures, compiler code generation, architectural performance evaluation and embedded computer systems. Conte is the past chair of the ACM Special Interest Group on Microarchitecture (SIGMICRO), the past chair of the IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture (TC-uARCH), and also a fellow of the IEEE. He was the editor in chief of the Journal of Instruction-Level Parallelism from 1997-2001 and 2002-2005. He is an associate editor of ACM Transactions on Embedded Computer Systems, ACM Transactions on Architecture and Compiler Optimization and IEEE Computer and IEEE Micro magazines. He is Professor of Computer Science and Director of the Center for Manycore Computing at Georgia Institute of Technology. Prior to this, he was on the faculty of NC State from 1995-2008.
Dr. Brian Flachs serves as architect, microarchitect and unit logic lead for the SPU Team (the special-purpose accelerator of CELL). He is interested in low latency-high frequency processors. Previously serving as microarchitect for IBM Austing Research Laboratories’ 1 GHz PowerPC Project. He earned his BSEE in 1988 from New Mexico State University and his MS and PhD in 1994 from Stanford University where he developed interests in computer architecture, image processing and machine learning.
This statement by Dave Patterson refers to the fact, that the manycore programming crisis is the most disruptive event in the entire history of computing. Most likely this can be solved only by hetero manycore architectures including both, traditional CPU cores, and, field-programmable accelerators.
Another key issue is, that, due to the von Neumann syndrome, our total computing ecosystem draws off a high percentage of the entire national electricity consumption (~30% in the US, and up to 50% are predicted). Seeing rapidly growing energy cost our computer-related infrastructure might become unaffordable. This might be another reason to go hetero.
These are dramatic challenges to future circuit, computer, and
systems design, as well as to CS-related curricula, which already
now miss the de facto job market. A sufficient number
of programmers and well acceptable tools for our manycore
future is not yet existing. What will the new roadmap look like?
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