ICCD 2009, October 2009,

ICCD 2009 Schedule Listed by Time

Sunday, October 4

16:00 Registration
17:00 Reception
18:00 END of Reception

Opening Ceremony
Monday, October 5, 9:00-9:15

Kee Sup Kim, Intel
Peter-Michael Seidel, AMD
Sofiene Tahar, Concordia University
Georgi Gaydadjiev, Delft University of Technology

Keynote I
Monday, October 5, 9:15-10:15

Larrabee: A Many-Core x86 Architecture for Visual Computing

Ed Grochowski
Intel Corporation

Session I
Monday, October 5, 10:45-12:00

 Invited Session organized by Davia J Lu, Intel Corporation 
Session 1.1 Disruptive Computing Technology (75 min)
Session Chair: Davia J Lu, Intel Corporation

Nishant Patil, Stanford University.
"Imperfection-Immune Carbon Nanotube Digital VLSI"

Bill Thies, Microsoft Research India.
"Computer-Aided Design for Microfluidic Chips Based on Multilayer Soft Lithography"

Naohiko Shimizu, IP ARCH, Inc. and Tokai University
“Reincarnate Historic Systems On FPGA with Novel Design Methodology”

 EDA Track 
Session 1.2 Advances in Timing Analysis and Optimization (75 min)
Session chair: Stephan Wong, TU Delft

Yang Xu and Ken Stevens.
"Automatic Synthesis of Computation Interference Constraints for Relative Timing Verification"

Renshen Wang, Takumi Okamoto and Chung-Kuan Cheng.
"Symmetrical Buffer Placement in Clock Trees for Minimal Skew Immune to Global On-chip Variations"

Aswin Sreedhar and Sandip Kundu.
"Statistical Timing Analysis based on simulation of Lithographic process"

 Computing Systems Track 
Session 1.3 System Power and Thermal Issues (75 min)
Session chair: Xiaoyao Liang, NVIDIA

Soumyaroop Roy, Nagarajan Ranganathan and Srinivas Katkoori.
"Compiler-Directed Leakage Reduction in Embedded Microprocessors"

Youngwoo Ahn, Inchoon Yeo and Riccardo Bettati.
"Efficient Calibration of Thermal Models based on Application Behavior"

Kyungtae Han, Zhen Fang, Richard Forand, Paul Diefenbaugh, Ravi Iyer and Donald Newell.
"Using Checksum to Reduce Power Consumption of the Display System for Low-Motion Content"

Session II
Monday, October 5, 13:30-15:35

 Transdisciplinary Tipping Points 
Session 2.1 Disruptive Computer Design (125 min)
Session chair: Jim Sproch, Synopsys

Massoud Pedram, USC
"Energy-Efficient Enterprise Computing."

Pradip Bose, IBM
"Technology-Aware Micro-architecture"

Edward Lee, Berkeley
"A Disruptive Computer Design Idea: Architectures with Repeatable Timing"

Uzi Vishkin
"Algorithmic Approach to Designing an Easy-To-Program System:
Can It Lead to a HW-Enhanced Programmer's Workflow Add-On?"

 Verification and Test Track 
Session 2.2 Hierarchical Testing and Design for Test (125 min)
Session chair: Prab Varma, Blue Pearl Software

Amit Nahar, Kenneth Butler, John Carulli and Charles Weinberger.
"Quality Improvement and Cost Reduction Using Statistical Outlier Methods"

Brandon Noia, Krishnendu Chakrabarty and Yuan Xie.
"Test-Wrapper Optimization for Embedded Cores in TSV-Based"

Matthieu Dubois, Haralampos-G. Stratigopoulos and Salvador Mir.
"Hierarchical Parametric Test Metrics Estimation: A Sigma-Delta Converter BIST Case-Study"

Xiaoyao Liang, Benjamin Lee, Gu-Yeon Wei and David Brooks.
"Design and Test Strategies for Microarchitectural Post-Fabrication Tuning"

short paper
Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas and Yiorgos Makris.
"Impact Analysis of Performance Faults in Modern Microprocessors"

short paper
Rajesh Kumar, Kalyana Bollapalli, Rajesh Garg, Tarun Soni and Sunil Khatri.
"A Robust Pulse-triggered Flip-Flop based Enhanced Scan Cell Design"

 Logic and Circuits Track 
Session 2.3 Clocking, Synchronization and Interconnect (125 min)
Session chair: Nestoras Tzartzanis, Apple

Saurabh Sinha, Wei Xu, Jyothi Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu and Yu Cao.
"Enabling Resonant Clock Distribution with Scaled On-Chip Magnetic Inductors"

Jean-Michel Chabloz and Ahmed Hemani.
"A Flexible Communication Scheme for Rationally-Related Clock Frequencies"

Navid Toosizadeh, Safwat G. Zaky and Jianwen Zhu.
"VariPipe: Low-overhead Variable-clock Synchronous Pipelines"

Masashi Imai, Tomohiro Yoneda and Takashi Nanya.
"N-way Ring and Square Arbiters"

Kalyana Bollapalli, Rajesh Garg, Kanupriya Gulati and Sunil Khatri.
"On-chip Bidirectional Wiring for Heavily Pipelined Systems using Network Coding"

Session III
Monday, October 5, 16:00-18:05

 Processor Architecture Track 
Session 3.1 Energy Efficient Architectures (125 min)
Session chair: Allen Cheng, University of Pittsburgh, US

Zichao Xie, Dong Tong and Xu Cheng.
"WHOLE: A Low Energy I-Cache with Separate Way History"

Weirong Jiang and Viktor Prasanna.
"Dynamic Power Reduction in Pipelined IP Forwarding Engines"

Salvador Petit, Rafael Ubal, Julio Sahuquillo and Pedro López.
"A Power-aware Hybrid RAM-CAM Renaming Mechanism for Fast Recovery"

Hai Lin and Yunsi Fei.
"Resource Sharing of Pipelined Custom Hardware Extension for Energy-efficient Application-specific Instruction Set Processor Design"

Nasir Mohyuddin, Kimish Patel and Massoud Pedram.
"Deterministic Clock Gating to Eliminate Wasteful Activity in Out-of-Order Superscalar Processors due to Wrong Path Instructions"

 Verification and Test Track 
Session 3.2 System Level Test and Verification (125 min)
Session chair: Kapila Udawatta, Intel Corporation

Vladimir Uzelac, Aleksandar Milenkovic, Milena Milenkovic and Martin Burtscher.
"Real-time, Unobtrusive, and Efficient Program Execution Tracing with Stream Caches and Last Stream Predictors"

Jason Lee, Praveen Bhojwani and Rabi Mahapatra.
"A Distributed Concurrent On-Line Test Scheduling Protocol for Many-Core NoC-Based Systems"

Amir Masoud Gharehbaghi and Masahiro Fujita.
"Transaction-Based Debugging of System-on-Chips with Patterns"

Robert Thacker, Chris Myers, Kevin Jones and Scott Little.
"A New Verification Method for Embedded Systems"

Rupsa Chakraborty and Dipanwita Roy Chowdhury.
"A Hierarchical Approach Towards System Level Static Timing Verification of SoCs"

 EDA Track 
Session 3.3 Synthesis and Optimization under Reliability Constraints (125 min)
Session chair: Mehdi Tahoori, North Eastern University

Jongyoon Jung and Taewhan Kim.
"Timing Variation-Aware High-Level Synthesis Considering Accurate Yield Computation"

Keven Woo and Matthew Guthaus.
"Fault-Tolerant Synthesis using Non-Uniform Redundancy"

Amit Berman and Idit Keidar.
"Low-Overhead Error Detection for Networks-on-Chip"

Amirali Shayan Arani, Xiang Hu, A. Ege Engin, Xiaoming Chen, Mikhail Popovich, Wanping Zhang and Chung-Kuan Cheng.
"Reliable 3D Stacked Power Distribution Considering Substrate Coupling"

Ravikishore Gandikota, David Blaauw and Dennis Sylvester.
"Interconnect Performance Corners considering Crosstalk Noise"

Conference Banquet and Keynote II
Monday, October 5, 18:30-21:00

Chair: Jim Sproch, Synopsys

Technology foundations and applications for contextual computing and combinatorial services.

Mike Liebhold
Senior Researcher
Institute For The Future

Keynote III
Tuesday, October 6, 9:00-10:00

What should one do with dark silicon?

Krisztian Flautner

Session IV
Tuesday, October 6, 10:30-12:05

 Processor Architecture Track 
Session 4.1 High Performance Architecture and Advanced Memory(125 min)
Session chair: Sung Woo Chung, Korea University., KR

Yusuke Tanaka and Hideki Ando.
"Reducing Register File Size through Instruction Pre-Execution Enhanced by Value Prediction"

Oscar Palomar, Toni Juan and Juan J. Navarro.
"Reusing cached schedules in an out-of-order processor with in-order issue logic"

Ahmed Al Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan and Yuan Xie.
"3D GPU Architecture using Cache Stacking: Performance, Cost, Power and Thermal analysis"

Suleyman Sair and Hanyu Cui.
"Extending Data Prefetching to Cope with Context Switch Misses"

Cheng-kok Koh, Weng-Fai Wong, Yiran Chen and Hai Li.
"The Salvage Cache: A fault-tolerant cache architecture for next-generation memory technologies"

 Computing Systems Track 
Session 4.2 Memory and Processors (125 min)
Session chair: John Kim, Cray / Northwestern Univ.

Javier Lira, Carlos Molina and Antonio González.
"LRU-PEA: A Smart Replacement Policy for Non-Uniform Cache Architectures on Chip Multiprocessors"

Jiayuan Meng and Kevin Skadron.
"Avoiding Cache Thrashing due to Private Data Placement in Last-level Cache For Manycore Scaling"

Siddhartha Chhabra, Brian Rogers and Yan Solihin.
"SHIELDSTRAP: Making Secure Processors Truly Secure"

Christophe Dubach, Timothy Jones and Michael O'Boyle.
"Rapid Early-Stage Microarchitecture Design Using Predictive Models"

Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su and Xiaoyu Li.
"Efficient Binary Translation System with Low Hardware Cost"

 Invited session organized by Rathish Jayabharathi, Intel Corporation. 
Session 4.3 Disruptive Trends in Test and Verification (125 min)
Session chair: Rathish Jayabharathi, Intel Corporation

Sule Ozev, Arizona State University
"Defect-Based Test Optimization for Analog/RF Circuits for Near-Zero DPPM Applications"

Abhijit Chatterjee, Georgia Tech
"Iterative Built-In Testing and Tuning of Mixed-Signal/RF Systems"

Krish Chakrabarty, Duke University
"Testing Bio-chips"

Hakan Baba, Dr. Kee Sup Kim, Intel Corporation
"Framework for Massively Parallel Testing at Wafer and Package Test"

Mehdi Tahoori, North Eastern
"Online Multiple Error Detection in Crossbar Nano-architectures"

Best Paper Session
Tuesday, October 6, 14:00-16:00

Session chairs: Sofiene Tahar, Concordia University
                           Georgi Gaydadjiev, Delft University of Technology

 Computer Systems Track 
Shantanu Gupta, Amin Ansari, Shuguang Feng and Scott Mahlke.
"Adaptive Online Testing for Efficient Hard Fault Detection"

 Processor Architecture Track 
Chun-Yi Lee and Niraj K. Jha.
"FinFET-based Dynamic Power Management of On-chip Interconnection Networks through Adaptive Back-gate Biasing"

 Logic and Circuits Track 
Xin Fan, Milos Krstic and Eckhard Grass.
"Analysis and Optimization of Pausible Clocking based GALS Design"

 Verification and Test Track 
Fahad Ahmed and Linda Milor.
"Reliable Cache Design with Detection of Gate Oxide Breakdown Using BIST"

 EDA Track 
This year none of the papers have qualified for the Best Paper Award for the EDA Track.

Session V
Wednesday, October 7, 8:30-10:00

 Logic and Circuits Track 
Session 5.1 Logic and Memory Design (90 min)
Session chair: Amy Novak, AMD

Lawrence Leinweber, Christos Papachristou and Francis G. Wolff.
"Efficient Architectures for Elliptic Curve Cryptographic Processors for RFID"

short paper
In-Cheol Park and Tae-Hwan Kim.
"Multiplier-less and Table-less Linear Approximation for Square and Square-root"

short paper
Sourabh Khire and Saibal Mukhopadhyay.
"On improving the algorithmic robustness of a low-power FIR filter"

Ajay Bhoj and Niraj Jha.
"Pragmatic Design of Gated-diode FinFET DRAMs"

short paper
Kristen Lovin, Benjamin Lee, Xiaoyao Liang, David Brooks and Gu-Yeon Wei.
"Empirical Performance Models for 3T1D Memories"

 Computing Systems Track 
Session 5.2 Application-optimized Systems (90 min)
Session chair: Pradip Bose, IBM

Jiawei Huang and John Lach.
"ColSpace: Towards Algorithm/Implementation Co-Optimization"

Chun He, Alexandros Papakonstantinou and Deming Chen.
"A Novel SoC Architecture on FPGA for Ultra Fast Face Detection"

Seung Eun Lee, Yong Zhang, Zhen Fang, Sadagopan Srinivasan, Ravi Iyer and Donald Newell.
"Accelerating Mobile Augmented Reality on a Handheld Platform"

Session VI
Wednesday, October 7, 10:30-12:35

 EDA Track 
Session 6.1 Novel Approaches to Synthesis and Simulation (125 min)
Session chair: Masahiro Fujita, University of Tokyo

Rance Rodrigues, Aswin Sreedhar and Sandip Kundu.
"Optical Lithography Simulation using Wavelet Transform"

Adam Kinsman and Nicola Nicolici.
"Computational Bit-width Allocation for Operations in Vector Calculus"

De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin and Yih-Lang Li.
"Topology-Driven Cell Layout Migration with Collinear Constraints"

Tsung-Wei Huang and Tsung-Yi Ho.
"A Fast Routability- and Performance-Driven Droplet Routing Algorithm for Digital Microfluidic Biochips"

Romana Fernandes and Ranga Vemuri.
"Accurate Estimation of Vector Dependent Leakage Power in the Presence of Process Variations"

 Processor Architecture Track 
Session 6.2 System Level Influence on Architecture (100 min)
Session chair: Hai Li, Polytechnic Institute of NYU, US, Chair

Vincent Weaver and Sally McKee.
"Code Density Concerns for New Architectures"

Michael J Anderson, Chuck Tsen, Liang-Kai Wang, Katherine Compton and Michael J Schulte.
"Performance Analysis of Decimal Floating-Point Libraries and Its Impact on Decimal Hardware and Software Solutions"

Hyung Beom Jang, Ikroh Yoon, Cheol Hong Kim, Seungwon Shin and Sung Woo Chung.
"The Impact of Liquid Cooling on 3D Multi-Core Processors"

short paper
Cor Meenderinck and Ben Juurlink.
"Intra-Vector SIMD Instructions for Core Specialization"

short paper
Shakeel Syed Abdulla, Nam Haewoon, Mark McDermott and Jacob Abraham.
"A High Throughput FFT Processor with no Multipliers"

 Logic and Circuits Track 
Session 6.3 Low Voltage and Low Power (125 min)
Session chair: Lars Svensson, Chalmers

Mateja Putic, Liang Di, Benton H. Calhoun and John C. Lach.
"Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design"

Rajesh Garg and Sunil Khatri.
"3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits"

Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal and Sunil Khatri.
"A Radiation Tolerant Phase Locked Loop Design for Digital Electronics"

Vinay Karkala, Kalyana Bollapalli, Rajesh Garg and Sunil Khatri.
"A PLL Design based on a Standing Wave Resonant Oscillator"

short paper
Bozena Kaminska.
"Mid-range Wireless Energy Transfer Using Inductive Resonance for Wireless Sensors"

short paper
Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai and Benton Calhoun.
"A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design Across Processes"

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