Oct 4-7 2009, Resort at Squaw Creek, Lake Tahoe, California
Sponsored by (IEEE pending*): IEEE Computer Society, IEEE Circuits and
Systems Society and IEEE Electron Devices Society
The pdf version of the Call for Papers can be found here
Submission deadline: May 11 (Extended deadline)
Final Manuscript Submission Deadline: May 18
Notification deadline: July 24
Final manuscript: August 24
The theme for ICCD 2009 is Disruptive Computer Design; submitted papers consistent with this theme are encouraged. Authors are invited to submit technical papers in accordance to the authors' instructions describing original work in one of the following areas:
Advanced computer architecture for general and application-specific enhancement; System design methods for uni- and parallel processors; Design methods for homogeneous and heterogeneous multi-core processor systems and system-on-chip designs; IP and platform-based designs; HW/SW co-design; Modeling and performance analysis; Support for security, languages and operating systems; Smart Cards; Real-time Systems; Application-specific and embedded software optimization; Optimizing and parallelizing compiler support for multithreaded and multi-core designs; Memory system and Network system optimization.
Microarchitecture design techniques for uni- and multi-core processors: instruction-level parallelism, pipelining, caching, branch prediction, multithreading, computer arithmetic; Techniques for low-power; secure, and reliable processor designs; Embedded, network, graphic, system-on-chip, application-specific and digital signal processor design; real-life design challenges: case studies, tradeoffs.
Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability and radiation; Design techniques for emerging process technologies (MEMs, spintronics, nano, quantum); Asynchronous circuits; Signal processing and arithmetic circuits, and circuits for graphic processor design.
High-level, logic and physical synthesis. Physical planning, design and early estimation for large circuits; Automatic analysis and optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and networks-on-chip; DfM and OPC methodologies; Tools, methodologies and design strate-gies for emerging technologies (MEMs, spintronics, nano, quantum).
Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Simulation-based and formal techniques for functional design verification; Dynamic simulation, equivalence checking, formal verification, model and property checking, and theorem proving; high-level design validation; hardware emulation, modeling languages, assertion-based verification, coverage-analysis, constrained-random test generation; design error debug and diagnosis; Hardware/Software validation; Fault modeling; Fault simulation and ATPG; Fault tolerance; DFT and BIST; SoC verification.
Carl Pixley, Synopsys
Kee Sup Kim, Intel
Peter-Michael Seidel, AMD
Technical Program Chairs
Georgi Gaydadjiev, TU Delft
Sofiene Tahar, Concordia University
Stephen Wong, TU Delft
Suleyman Sair, North Carolina State University
Elaheh Bozorgzadeh, UC Irvine
Special Sessions Chair
Srikanath Venkataraman, Intel
Jim Sproch, Synopsis
Nam Sung Kim, UW Madison
Ben Juurlink, TU Delft
Local Arrangement Chair
Hussain Al-Assad, UC Davis
Computer Systems Design and Applications Track
Greg Byrd, NC State University
Michael Gschwind, IBM
Processor Architecture Track
Jim Bondi, Texas Instruments
Eren Kursun, IBM
Logic and Circuit Design Track
Lars Svensson, Chalmers University of Technology, Sweden
Guy Even, Tel Aviv University
Electronic Design Automation Track
Jorg Henkel, University of Karlshrue
Farzan Fallah, Envis
Verification and Test Track
Sule Ozev, Arizona State University
Klaus Schneider, University of Kaiserslautern
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