ICCD 2010, October 2010,
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Computational Models for the
Age of Multicore Processing

Monday, October 4, 9:15-10:15


Wolfgang Paul
Saarland University


Abstract:

Industry is presently investigating the possibility to use commodity multicore processors connected by standard network components in safety critical systems like cars.

In this scenario one clearly wants to be able to argue that a passenger on the rear seat trying to hack the car's entertainment system cannot shoot down the electronic chassis control and the engine control, although large portions of the hardware are shared. Any such argument - be it informal, a paper and pencil proof, or formally verified by a CAV system - has to consider the layers of the architecture of the car's computer system; it has to show that each layer provides a simulation between two adjacent computational models in the systems architecture and that these simulated models stay intact for all configurations and input sequences of the entire system.

These models turn out to be far from obvious with very subtle and nontrivial modifications compared to classical textbook computer science.

In this talk we will give an overview of the models involved and the arguments justifying the simulation theorems between the system layers.

Clearly, we will not be able to go into deep details about the arguments, but after the talk, members of the audience should be able to answer questions like

  1. Where is the mechanism for clock synchronization in a time triggered system implemented?
    • in the software of the real time operating system
    • in the hardware of the bus interfaces.
  2. Where is the mechanism for locking in a multicore system implemented?
    • in the processor hardware
    • in the compiler
    • in the operating system software.


Bio:

Wolfgang Paul was born in 1951. At age 22 he completed his PhD in theoretical computer science at Saarland University. He was a post doc at Cornell University working in complexity theory and then became a tenured associate professor of mathematics at the University of Bielefeld at age 25. After finishing a professional cooking degree at a Michelin 1 star restaurant he worked from 1982 to 1986 as a research staff member in the theory group and the physics department of IBMs Almaden Research Lab. Since 1986 he is a full professor for Computer Architecture and Parallel Computing at Saarland University, where he served as chairman of computer science, dean of engineering and acting head of the universities computing center. From 2003 to 2007 he was the scientific coordinator of projects 'Verisoft' and 'Verisoft-XT', two large projects aiming at the pervasive formal verification of entire computer systems from the gate level to the applications. Wolfgang Paul holds an honorary doctorate degree from Pacific State University (Russia) and is a member of Academia Europeae. So far Wolfgang Paul has graduated 52 PhD students many of which had distinguished careers in academia and in industry. He has 2 children from 3 marriages.

 


Automotive Embedded Driver Assistance: A Real-Time Low-Power FPGA Stereo Engine using Semi-Global Matching

Monday, October 4, 16:15-17:00


Felix Eberli
Supercomputing Systems AG, Zurich, Switzerland


Abstract:

Today, automotive driver assistant systems are a growing market. After an overview on current driver assistant systems we will focus on vision based systems and their special requirements. As an example project we will describe the development of a next generation stereo vision algorithm.

Example project: Many real-time stereo vision systems are available on low-power platforms. However, when looking at high-performance global stereo methods as listed in the upper third of the Middleburry database, the low-power real-time implementations for these methods were still missing. We proposed (ICVS 2009) a real-time implementation (25fps / 640x400 / up to a maximum of 128 disparities) of the semi-global matching algorithm with algorithmic extensions for automotive applications on a reconfigurable hardware platform (FPGA) resulting in a low power consumption of under 3W.


Bio:

Felix Eberli is a Department Head at Supercomputing Systems AG in Zurich, Switzerland. After working for Phonak as an ASIC engineer, Felix joined SCS in 2002 and leads the embedded automotive department. As a contract developer he worked on projects for HP in the supercomputing area and has expertise in development of next generation driver assistant systems with major automotive OEM and Tier1.

 


Recent Additions to the ARMv7-A Architecture

Tuesday, October 5, 8:30-9:30


David Brash
ARM


Abstract:

This talk will be based on recent announcements regarding new address translation and virtualization support in the ARM architecture. It will also raise awareness around the promise of new power/performance points and opportunities that are expected from the first ARM implementation, the Cortex-A15 core.


Bio:

David Brash joined ARM in 1998 and was appointed Architecture Program Manager in 2000. His responsibilities include chairing the Architecture Review Board, evangelism, development and delivery of the ARM Architecture specifications, encouraging early adoption e.g. Operating System (OS) ports, and working with lead partners and OEM’s to develop future enhancements.

David started his career with Racal developing government and military communications equipment. He then joined Digital Equipment Company (DEC) to design backbone router and infrastructure products. David was promoted to Consultant Engineer and started a European systems engineering group to provide boards, tools and firmware support for Digital's semiconductor division. The group was involved with Digital's Alpha processor, PCI, and StrongARM products.

David graduated from the University of Strathclyde with a BSc in Electrical and Electronic Engineering, and holds 2 patents from his time with Digital.



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