Keynote Speakers
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Gigascale System
Design-Challenges & Opportunities
Shekhar Borkar -
Error-Tolerance
Melvin A. Breuer -
Digital Integrated
Circuit Testing for Art Historians and Test Experts
1.1 High-Speed and Energy-Efficient Circuit Design
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PCAM: A Ternary CAM Optimized for Longest Prefix Matching
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Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip
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An Area- and Energy-Efficient Asynchronous Booth Multiplier for
Mobile Devices
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A High-Frequency Decimal Multiplier
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An Efficient Twin-Precision Multiplier
1.2 Energy-Efficient Processor Microarchitecture (1)
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Defining Wakeup Width for Efficient Dynamic Scheduling
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Power-Aware Deterministic Block Allocation for Low-Power Way-Selective
Cache Structure
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Thermal-Aware Clustered Microarchitectures
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Reducing Issue Queue Power for Multimedia Applications using a Feedback
Control Algorithm
1.3 Scan Design and Test
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A Novel Low-Power Scan Design Technique Using Supply Gating
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Asynchronous Scan-Latch controller for Low Area Overhead DFT
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End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths
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Functional Illinois Scan Design at RTL
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On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan
2.1 Routing and Floorplanning
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A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for
VLSI Circuits
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Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in
Global Routing
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A Two-Layer Bus Routing Algorithm for High-Speed Boards
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Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers
2.2 Formal Verification Embedded Tutorial
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Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model
Checking
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Comparative Study of Strategies for Formal Verification of High-Level
Processors
2.3 Signal Integrity and Leakage
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A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS
Circuits
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A Signal Integrity Test Bed for PCB Buses
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A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in
On-Chip Repeaters
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A General Post-Processing Approach to Leakage Current Reduction in
SRAM-Based FPGAs
3.1 Special Session on High-Performance On-Chip Communication
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Design Methodologies and Architecture Solutions for High-Performance
Interconnects
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On-Chip Transparent Wire Pipelining
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Toward an Integrated Design Methodology
for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
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Network-on-Chip: The Intelligence Is In The Wire
3.2 Test Generation and Characterization
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Low Power Test Data Compression Based on LFSR Reseeding
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An Infrastructure IP for On-Chip Clock Jitter Measurement
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Diagnosis of Hold Time Defects
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Extending the Applicability of Parallel-Serial Scan Designs
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Quality Improvement Methods for System-Level Stimuli Generation
3.3 Physically-Aware Design Tools
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XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
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A Flexible Data Structure for Efficient Buffer Insertion
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Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of
Vertically Integrated 3D Systems
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Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
4.1 Energy-Efficient Processor Microarchitecture (2)
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Best of Both Latency and Throughput
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Fetch Halting on Critical Load Misses
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Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2
4.2 Power and Timing Optimization
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Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
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Potential Slack Budgeting with Clock Skew Optimiza
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A New Statistical Optimization Algorithm for Gate Sizing
4.3 Novel Processor Design
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An Architecture for Fast Processing of Large Unstructured Data Sets
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In-System FPGA Prototyping of an Itanium Microarchitechture
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Adaptive Selection of
an Index in a Texture Cache
5.1 Emerging Technologies Special Session
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Using Circuits and Systems-Level Research to Drive Nanotechnology
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FPGA Emulation of Quantum Circuits
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3D Processing Technology and Its Impact on iA32 Microprocessors
5.2 Cache Memory Design
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Cache Array Architecture Optimization at Deep Submicron Technologies
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Implementation of Fine-Grained Cache Monitoring for Improved SMT
Scheduling
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Low Energy, Highly-Associative Cache Design for Embedded Processors
6.1 Layout-Driven Circuit Optimization
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The Magic of a Via-Configurable Regular Fabric
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A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
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Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
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Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power &
High-Speed
6.2 Instruction-Level Parallelism (1)
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A Minimal Dual-Core Speculative Multi-Threading Architecture
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Exploiting Quiescent States in Register Lifetime
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Evaluating Techniques for Exploiting Instruction Slack
6.3 Power Estimation and Minimization
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Static Transition Probability Analysis Under Uncertainty
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Circuit-Based Preprocessing of ILP and Its Applications in Leakage
Minimization and Power Estimation
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Analyzing Power Consumption of Message Passing Primitives in a Single-Chip
Multiprocessor
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An
Architectural Power Estimator for Analog-to-Digital Converters
7.1 Formal Verification Techniques
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Formal Hardware Verification based on Signal Correlation Properties
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Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs
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Graph Automorphism-Based Algorithm for Determining Symmetric Inputs
7.2 Networks on Chips
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Linear Programming based Techniques for Synthesis of Network-on-Chip
Architectures
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Thermal-Aware IP Virtualization and Placement for Networks-on-Chip
Architecture
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Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
7.3 Novel Processor Architecture
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An Embedded Reconfigurable SIMD DSP with Capability of
Dimension-Controllable Vector Processing
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Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code
Execution
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Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study
8.1 Instruction-Level Parallelism (2)
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Compiler-Based Frame Formation for Static Optimization
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IPC Driven Dynamic Associative Cache Architecture for
Low Energy
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Increasing Processor Performance Through Early
Register Release
8.2 Topics in Synthesis and Co-Simulation
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Combined Channel Segmentation and Buffer Insertion for Routability and
Performance Improvement of Field Programmable Analog Arrays
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Software/Network Co-Simulation of Heterogeneous Industrial Networks
Architectures
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Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing
Elements using SystemC
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Coping with The Variability of Combinational Logic Delays
8.3 Low-Power Architecture
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Design-Space Exploration of Power-Aware On/Off Interconnection Networks
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Energy Characterization of Hardware-Based Data
Prefetching
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Design and Implementation of Scalable Low-Power
Montgomery Multiplier
9.1 Test Generation
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Compressed Embedded Diagnosis of Logic Cores
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An Automatic Test Pattern Generation Framework for
Combinational Threshold Logic Networks
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An Efficient Algorithm for Reconfiguring Shared Spare
RRAM
9.2 Network Routing
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An
Accurate Combinatorial Model for Performance Prediction of Deterministic
Wormhole Routing in Torus Multicomputer Systems
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Technique to Eliminate Sorting in IP Packet Forwarding
Devices
9.3 Placement and Floorplanning
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I/O
Clustering in Design Cost and Performance Optimization for Flip-Chip
Design
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Placement with Alignment and Performance Constraints
Using the B*-Tree Representation
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ACG-Adjacent Constraint Graph for General Floorplans